Commit 7181f718 authored by Yeoreum Yun's avatar Yeoreum Yun Committed by Catalin Marinas
Browse files

arm64: cpufeature: Add FEAT_LSUI 



Since Armv9.6, FEAT_LSUI introduces atomic instructions that allow
privileged code to access user memory without clearing the PSTATE.PAN
bit. Add CPU feature detection for FEAT_LSUI.

Signed-off-by: default avatarYeoreum Yun <yeoreum.yun@arm.com>
[catalin.marinas@arm.com: Remove commit log references to SW_PAN]
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 1f318b96

arch/arm64/include/asm/cpucaps.h

+2 −0
Original line number Diff line number Diff line
@@ -71,6 +71,8 @@ cpucap_is_possible(const unsigned int cap) 
		return true;

	case ARM64_HAS_PMUV3:

		return IS_ENABLED(CONFIG_HW_PERF_EVENTS);

	case ARM64_HAS_LSUI:

		return IS_ENABLED(CONFIG_ARM64_LSUI);

	}



	return true;

arch/arm64/kernel/cpufeature.c

+10 −0
Original line number Diff line number Diff line
@@ -281,6 +281,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 


static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),

	ARM64_FTR_END,
@@ -3169,6 +3170,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.cpu_enable = cpu_enable_ls64_v,

		ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V)

	},

#ifdef CONFIG_ARM64_LSUI

	{

		.desc = "Unprivileged Load Store Instructions (LSUI)",

		.capability = ARM64_HAS_LSUI,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP)

	},

#endif

	{},

};

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ HAS_LPA2 
HAS_LSE_ATOMICS

HAS_LS64

HAS_LS64_V

HAS_LSUI

HAS_MOPS

HAS_NESTED_VIRT

HAS_BBML2_NOABORT