Commit 720e4a4a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-renesas', 'clk-kunit', 'clk-regmap' and 'clk-frac-divider' into clk-next

 - Make clk kunit tests work with lockdep
 - Fix clk gate kunit test for big-endian
 - Convert more than a handful of clk drivers to use regmap maple tree
 - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
   implementation

* clk-renesas: (23 commits)
  clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
  clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
  clk: renesas: Add minimal boot support for RZ/G3S SoC
  clk: renesas: rzg2l: Add divider clock for RZ/G3S
  clk: renesas: rzg2l: Refactor SD mux driver
  clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
  clk: renesas: rzg2l: Add struct clk_hw_data
  clk: renesas: rzg2l: Add support for RZ/G3S PLL
  clk: renesas: rzg2l: Remove critical area
  clk: renesas: rzg2l: Fix computation formula
  clk: renesas: rzg2l: Trust value returned by hardware
  clk: renesas: rzg2l: Lock around writes to mux register
  clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
  clk: renesas: rcar-gen3: Extend SDnH divider table
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
  clk: renesas: r8a7795: Constify r8a7795_*_clks
  clk: renesas: r9a06g032: Name anonymous structs
  clk: renesas: r9a06g032: Fix kerneldoc warning
  clk: renesas: rzg2l: Use u32 for flag and mux_flags
  clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
  ...

* clk-kunit:
  clk: Fix clk gate kunit test on big-endian CPUs
  clk: Parameterize clk_leaf_mux_set_rate_parent
  clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops

* clk-regmap:
  clk: versaclock7: Convert to use maple tree register cache
  clk: versaclock5: Convert to use maple tree register cache
  clk: versaclock3: Convert to use maple tree register cache
  clk: versaclock3: Remove redundant _is_writeable()
  clk: si570: Convert to use maple tree register cache
  clk: si544: Convert to use maple tree register cache
  clk: si5351: Convert to use maple tree register cache
  clk: si5341: Convert to use maple tree register cache
  clk: si514: Convert to use maple tree register cache
  clk: cdce925: Convert to use maple tree register cache

* clk-frac-divider:
  clk: fractional-divider: tests: Add test suite for edge cases
  clk: fractional-divider: Improve approximation when zero based and export
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+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties:
      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
      - renesas,r9a07g044-cpg # RZ/G2{L,LC}
      - renesas,r9a07g054-cpg # RZ/V2L
      - renesas,r9a08g045-cpg # RZ/G3S
      - renesas,r9a09g011-cpg # RZ/V2M

  reg:
+1 −0
Original line number Diff line number Diff line
@@ -2,4 +2,5 @@ CONFIG_KUNIT=y
CONFIG_COMMON_CLK=y
CONFIG_CLK_KUNIT_TEST=y
CONFIG_CLK_GATE_KUNIT_TEST=y
CONFIG_CLK_FD_KUNIT_TEST=y
CONFIG_UML_PCI_OVER_VIRTIO=n
+7 −0
Original line number Diff line number Diff line
@@ -526,4 +526,11 @@ config CLK_GATE_KUNIT_TEST
	help
	  Kunit test for the basic clk gate type.

config CLK_FD_KUNIT_TEST
	tristate "Basic fractional divider type Kunit test" if !KUNIT_ALL_TESTS
	depends on KUNIT
	default KUNIT_ALL_TESTS
	help
	  Kunit test for the clk-fractional-divider type.

endif
+1 −0
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@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
obj-$(CONFIG_COMMON_CLK)	+= clk-fractional-divider.o
obj-$(CONFIG_CLK_FD_KUNIT_TEST) += clk-fractional-divider_test.o
obj-$(CONFIG_COMMON_CLK)	+= clk-gpio.o
ifeq ($(CONFIG_OF), y)
obj-$(CONFIG_COMMON_CLK)	+= clk-conf.o
+1 −1
Original line number Diff line number Diff line
@@ -647,7 +647,7 @@ static int cdce925_probe(struct i2c_client *client)
		.name = "configuration0",
		.reg_bits = 8,
		.val_bits = 8,
		.cache_type = REGCACHE_RBTREE,
		.cache_type = REGCACHE_MAPLE,
	};

	dev_dbg(&client->dev, "%s\n", __func__);
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