Commit 721f791c authored by Uros Bizjak's avatar Uros Bizjak Committed by Ingo Molnar
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x86/boot: Use 32-bit XOR to clear registers



x86_64 zero extends 32-bit operations, so for 64-bit operands,
XORL r32,r32 is functionally equal to XORQ r64,r64, but avoids
a REX prefix byte when legacy registers are used.

Slightly smaller code generated, no change in functionality.

Signed-off-by: default avatarUros Bizjak <ubizjak@gmail.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20240124103859.611372-1-ubizjak@gmail.com
parent 891f8890
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+3 −3
Original line number Diff line number Diff line
@@ -169,7 +169,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
	ANNOTATE_NOENDBR

	/* Clear %R15 which holds the boot_params pointer on the boot CPU */
	xorq	%r15, %r15
	xorl	%r15d, %r15d

	/*
	 * Retrieve the modifier (SME encryption mask if SME is active) to be
@@ -178,7 +178,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
#ifdef CONFIG_AMD_MEM_ENCRYPT
	movq	sme_me_mask, %rax
#else
	xorq	%rax, %rax
	xorl	%eax, %eax
#endif

	/* Form the CR3 value being sure to include the CR3 modifier */
@@ -295,7 +295,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)

.Llookup_AP:
	/* EAX contains the APIC ID of the current CPU */
	xorq	%rcx, %rcx
	xorl	%ecx, %ecx
	leaq	cpuid_to_apicid(%rip), %rbx

.Lfind_cpunr:
+1 −1
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ SYM_FUNC_START(sev_verify_cbit)
	 * The check failed, prevent any forward progress to prevent ROP
	 * attacks, invalidate the stack and go into a hlt loop.
	 */
	xorq	%rsp, %rsp
	xorl	%esp, %esp
	subq	$0x1000, %rsp
2:	hlt
	jmp 2b