Commit 732c35ce authored by Shravan Kumar Ramani's avatar Shravan Kumar Ramani Committed by Hans de Goede
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platform/mellanox: mlxbf-pmc: Fix offset calculation for crspace events 



The event selector fields for 2 counters are contained in one
32-bit register and the current logic does not account for this.

Fixes: 423c3361 ("platform/mellanox: mlxbf-pmc: Add support for BlueField-3")
Signed-off-by: default avatarShravan Kumar Ramani <shravankr@nvidia.com>
Reviewed-by: default avatarDavid Thompson <davthompson@nvidia.com>
Reviewed-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Link: https://lore.kernel.org/r/8834cfa496c97c7c2fcebcfca5a2aa007e20ae96.1705485095.git.shravankr@nvidia.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 8cbc756b

drivers/platform/mellanox/mlxbf-pmc.c

+2 −2
Original line number Diff line number Diff line
@@ -1170,7 +1170,7 @@ static int mlxbf_pmc_program_crspace_counter(int blk_num, uint32_t cnt_num, 
	int ret;



	addr = pmc->block[blk_num].mmio_base +

		(rounddown(cnt_num, 2) * MLXBF_PMC_CRSPACE_PERFSEL_SZ);

		((cnt_num / 2) * MLXBF_PMC_CRSPACE_PERFSEL_SZ);

	ret = mlxbf_pmc_readl(addr, &word);

	if (ret)

		return ret;
@@ -1413,7 +1413,7 @@ static int mlxbf_pmc_read_crspace_event(int blk_num, uint32_t cnt_num, 
	int ret;



	addr = pmc->block[blk_num].mmio_base +

		(rounddown(cnt_num, 2) * MLXBF_PMC_CRSPACE_PERFSEL_SZ);

		((cnt_num / 2) * MLXBF_PMC_CRSPACE_PERFSEL_SZ);

	ret = mlxbf_pmc_readl(addr, &word);

	if (ret)

		return ret;