Commit 73302562 authored by Natalie Vock's avatar Natalie Vock Committed by Alex Deucher
Browse files

drm/amdgpu: Reset IH OVERFLOW_CLEAR bit 



Allows us to detect subsequent IH ring buffer overflows as well.

Cc: Joshua Ashton <joshua@froggi.es>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarFriedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4f56acde

drivers/gpu/drm/amd/amdgpu/cik_ih.c

+6 −0
Original line number Diff line number Diff line
@@ -204,6 +204,12 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev, 
		tmp = RREG32(mmIH_RB_CNTL);

		tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;

		WREG32(mmIH_RB_CNTL, tmp);



		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows

		 * can be detected.

		 */

		tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;

		WREG32(mmIH_RB_CNTL, tmp);

	}

	return (wptr & ih->ptr_mask);

}

drivers/gpu/drm/amd/amdgpu/cz_ih.c

+5 −0
Original line number Diff line number Diff line
@@ -216,6 +216,11 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev, 
	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

	WREG32(mmIH_RB_CNTL, tmp);



	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows

	 * can be detected.

	 */

	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

	WREG32(mmIH_RB_CNTL, tmp);



out:

	return (wptr & ih->ptr_mask);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

+5 −0
Original line number Diff line number Diff line
@@ -215,6 +215,11 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev, 
	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

	WREG32(mmIH_RB_CNTL, tmp);



	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows

	 * can be detected.

	 */

	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

	WREG32(mmIH_RB_CNTL, tmp);



out:

	return (wptr & ih->ptr_mask);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

+6 −0
Original line number Diff line number Diff line
@@ -418,6 +418,12 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev, 
	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);



	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows

	 * can be detected.

	 */

	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);

out:

	return (wptr & ih->ptr_mask);

}

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

+7 −0
Original line number Diff line number Diff line
@@ -418,6 +418,13 @@ static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev, 
	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);

	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);



	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows

	 * can be detected.

	 */

	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);



out:

	return (wptr & ih->ptr_mask);

}