Commit 739f04f4 authored by Shawn Lin's avatar Shawn Lin Committed by Ulf Hansson
Browse files

mmc: dw_mmc-rockchip: Fix wrong internal phase calculate 



ciu clock is 2 times of io clock, but the sample clk used is
derived from io clock provided to the card. So we should use
io clock to calculate the phase.

Fixes: 59903441 ("mmc: dw_mmc-rockchip: Add internal phase support")
Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 9e805625

drivers/mmc/host/dw_mmc-rockchip.c

+2 −2
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ struct dw_mci_rockchip_priv_data { 
 */

static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample)

{

	unsigned long rate = clk_get_rate(host->ciu_clk);

	unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;

	u32 raw_value;

	u16 degrees;

	u32 delay_num = 0;
@@ -85,7 +85,7 @@ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) 


static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees)

{

	unsigned long rate = clk_get_rate(host->ciu_clk);

	unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;

	u8 nineties, remainder;

	u8 delay_num;

	u32 raw_value;