Commit 73c4699a authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'spi-nor/for-6.16' into mtd/next 

SPI NOR changes for 6.16

Notable changes:

- Cleanup some Macronix flash entries.

- Add SFDP table fixups for Macronix MX25L3255E.
parents 0aa7b390 594c8df9

drivers/mtd/spi-nor/macronix.c

+39 −34
Original line number Diff line number Diff line
@@ -58,6 +58,31 @@ macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor) 
	return 0;

}



static int

mx25l3255e_late_init_fixups(struct spi_nor *nor)

{

	struct spi_nor_flash_parameter *params = nor->params;



	/*

	 * SFDP of MX25L3255E is JESD216, which does not include the Quad

	 * Enable bit Requirement in BFPT. As a result, during BFPT parsing,

	 * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.

	 * Therefore, it is necessary to correct this setting by late_init.

	 */

	params->quad_enable = spi_nor_sr1_bit6_quad_enable;



	/*

	 * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte

	 * address mode. However, since the 3-byte address 1-4-4 page program

	 * is not defined in SFDP, it needs to be configured in late_init.

	 */

	params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4;

	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_4_4],

				SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);



	return 0;

}



static const struct spi_nor_fixups mx25l25635_fixups = {

	.post_bfpt = mx25l25635_post_bfpt_fixups,

	.post_sfdp = macronix_qpp4b_post_sfdp_fixups,
@@ -67,6 +92,10 @@ static const struct spi_nor_fixups macronix_qpp4b_fixups = { 
	.post_sfdp = macronix_qpp4b_post_sfdp_fixups,

};



static const struct spi_nor_fixups mx25l3255e_fixups = {

	.late_init = mx25l3255e_late_init_fixups,

};



static const struct flash_info macronix_nor_parts[] = {

	{

		.id = SNOR_ID(0xc2, 0x20, 0x10),
@@ -88,10 +117,8 @@ static const struct flash_info macronix_nor_parts[] = { 
		.name = "mx25l8005",

		.size = SZ_1M,

	}, {

		/* MX25L1606E */

		.id = SNOR_ID(0xc2, 0x20, 0x15),

		.name = "mx25l1606e",

		.size = SZ_2M,

		.no_sfdp_flags = SECT_4K,

	}, {

		.id = SNOR_ID(0xc2, 0x20, 0x16),

		.name = "mx25l3205d",
@@ -103,29 +130,21 @@ static const struct flash_info macronix_nor_parts[] = { 
		.size = SZ_8M,

		.no_sfdp_flags = SECT_4K,

	}, {

		/* MX25L12805D */

		.id = SNOR_ID(0xc2, 0x20, 0x18),

		.name = "mx25l12805d",

		.size = SZ_16M,

		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,

		.no_sfdp_flags = SECT_4K,

	}, {

		/* MX25L25635E, MX25L25645G */

		.id = SNOR_ID(0xc2, 0x20, 0x19),

		.name = "mx25l25635e",

		.size = SZ_32M,

		.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

		.fixups = &mx25l25635_fixups

	}, {

		/* MX66L51235F */

		.id = SNOR_ID(0xc2, 0x20, 0x1a),

		.name = "mx66l51235f",

		.size = SZ_64M,

		.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

		.fixup_flags = SPI_NOR_4B_OPCODES,

		.fixups = &macronix_qpp4b_fixups,

	}, {

		/* MX66L1G45G */

		.id = SNOR_ID(0xc2, 0x20, 0x1b),

		.name = "mx66l1g45g",

		.size = SZ_128M,

		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

		.fixups = &macronix_qpp4b_fixups,

	}, {

		/* MX66L2G45G */
@@ -167,29 +186,16 @@ static const struct flash_info macronix_nor_parts[] = { 
		.size = SZ_16M,

		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

	}, {

		/* MX25U51245G */

		.id = SNOR_ID(0xc2, 0x25, 0x3a),

		.name = "mx25u51245g",

		.size = SZ_64M,

		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

		.fixup_flags = SPI_NOR_4B_OPCODES,

		.fixups = &macronix_qpp4b_fixups,

	}, {

		.id = SNOR_ID(0xc2, 0x25, 0x3a),

		.name = "mx66u51235f",

		.size = SZ_64M,

		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

		.fixup_flags = SPI_NOR_4B_OPCODES,

		.fixups = &macronix_qpp4b_fixups,

	}, {

		/* MX66U1G45G */

		.id = SNOR_ID(0xc2, 0x25, 0x3b),

		.fixups = &macronix_qpp4b_fixups,

	}, {

		/* MX66U2G45G */

		.id = SNOR_ID(0xc2, 0x25, 0x3c),

		.name = "mx66u2g45g",

		.size = SZ_256M,

		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

		.fixup_flags = SPI_NOR_4B_OPCODES,

		.fixups = &macronix_qpp4b_fixups,

	}, {

		.id = SNOR_ID(0xc2, 0x26, 0x18),
@@ -215,15 +221,14 @@ static const struct flash_info macronix_nor_parts[] = { 
		.size = SZ_4M,

		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,

	}, {

		/* MX25UW51245G */

		.id = SNOR_ID(0xc2, 0x81, 0x3a),

		.name = "mx25uw51245g",

		.n_banks = 4,

		.flags = SPI_NOR_RWW,

	}, {

		/* MX25L3255E */

		.id = SNOR_ID(0xc2, 0x9e, 0x16),

		.name = "mx25l3255e",

		.size = SZ_4M,

		.no_sfdp_flags = SECT_4K,

		.fixups = &mx25l3255e_fixups,

	},

	/*

	 * This spares us of adding new flash entries for flashes that can be