Commit 7405c0f0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-urgent-2025-03-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull misc x86 fixes and updates from Ingo Molnar:

 - Fix a large number of x86 Kconfig dependency and help text accuracy
   bugs/problems, by Mateusz Jończyk and David Heideberg

 - Fix a VM_PAT interaction with fork() crash. This also touches core
   kernel code

 - Fix an ORC unwinder bug for interrupt entries

 - Fixes and cleanups

 - Fix an AMD microcode loader bug that can promote verification
   failures into success

 - Add early-printk support for MMIO based UARTs on an x86 board that
   had no other serial debugging facility and also experienced early
   boot crashes

* tag 'x86-urgent-2025-03-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/microcode/AMD: Fix __apply_microcode_amd()'s return value
  x86/mm/pat: Fix VM_PAT handling when fork() fails in copy_page_range()
  x86/fpu: Update the outdated comment above fpstate_init_user()
  x86/early_printk: Add support for MMIO-based UARTs
  x86/dumpstack: Fix inaccurate unwinding from exception stacks due to misplaced assignment
  x86/entry: Fix ORC unwinder for PUSH_REGS with save_ret=1
  x86/Kconfig: Fix lists in X86_EXTENDED_PLATFORM help text
  x86/Kconfig: Correct X86_X2APIC help text
  x86/speculation: Remove the extra #ifdef around CALL_NOSPEC
  x86/Kconfig: Document release year of glibc 2.3.3
  x86/Kconfig: Make CONFIG_PCI_CNB20LE_QUIRK depend on X86_32
  x86/Kconfig: Document CONFIG_PCI_MMCONFIG
  x86/Kconfig: Update lists in X86_EXTENDED_PLATFORM
  x86/Kconfig: Move all X86_EXTENDED_PLATFORM options together
  x86/Kconfig: Always enable ARCH_SPARSEMEM_ENABLE
  x86/Kconfig: Enable X86_X2APIC by default and improve help text
parents b4c5c57c 31ab12df

Documentation/admin-guide/kernel-parameters.txt

+8 −1
Original line number Diff line number Diff line
@@ -1407,14 +1407,21 @@ 
			earlyprintk=serial[,0x...[,baudrate]]

			earlyprintk=ttySn[,baudrate]

			earlyprintk=dbgp[debugController#]

			earlyprintk=pciserial[,force],bus:device.function[,baudrate]

			earlyprintk=pciserial[,force],bus:device.function[,{nocfg|baudrate}]

			earlyprintk=xdbc[xhciController#]

			earlyprintk=bios

			earlyprintk=mmio,membase[,{nocfg|baudrate}]



			earlyprintk is useful when the kernel crashes before

			the normal console is initialized. It is not enabled by

			default because it has some cosmetic problems.



			Only 32-bit memory addresses are supported for "mmio"

			and "pciserial" devices.



			Use "nocfg" to skip UART configuration, assume

			BIOS/firmware has configured UART correctly.



			Append ",keep" to not disable it when the real console

			takes over.

arch/x86/Kconfig

+56 −27
Original line number Diff line number Diff line
@@ -460,20 +460,28 @@ config SMP 
	  If you don't know what to do here, say N.



config X86_X2APIC

	bool "Support x2apic"

	bool "x2APIC interrupt controller architecture support"

	depends on X86_LOCAL_APIC && X86_64 && (IRQ_REMAP || HYPERVISOR_GUEST)

	default y

	help

	  This enables x2apic support on CPUs that have this feature.

	  x2APIC is an interrupt controller architecture, a component of which

	  (the local APIC) is present in the CPU. It allows faster access to

	  the local APIC and supports a larger number of CPUs in the system

	  than the predecessors.



	  This allows 32-bit apic IDs (so it can support very large systems),

	  and accesses the local apic via MSRs not via mmio.

	  x2APIC was introduced in Intel CPUs around 2008 and in AMD EPYC CPUs

	  in 2019, but it can be disabled by the BIOS. It is also frequently

	  emulated in virtual machines, even when the host CPU does not support

	  it. Support in the CPU can be checked by executing

		grep x2apic /proc/cpuinfo



	  Some Intel systems circa 2022 and later are locked into x2APIC mode

	  and can not fall back to the legacy APIC modes if SGX or TDX are

	  enabled in the BIOS. They will boot with very reduced functionality

	  without enabling this option.

	  If this configuration option is disabled, the kernel will boot with

	  very reduced functionality and performance on some platforms that

	  have x2APIC enabled. On the other hand, on hardware that does not

	  support x2APIC, a kernel with this option enabled will just fallback

	  to older APIC implementations.



	  If you don't know what to do here, say N.

	  If in doubt, say Y.



config X86_POSTED_MSI

	bool "Enable MSI and MSI-x delivery by posted interrupts"
@@ -544,16 +552,17 @@ config X86_EXTENDED_PLATFORM 
	  CONFIG_64BIT.



	  32-bit platforms (CONFIG_64BIT=n):

		Goldfish (Android emulator)

		AMD Elan

		Goldfish (mostly Android emulator)

		Intel CE media processor (CE4100) SoC

		Intel Quark

		RDC R-321x SoC

		SGI 320/540 (Visual Workstation)



	  64-bit platforms (CONFIG_64BIT=y):

		Numascale NumaChip

		ScaleMP vSMP

		SGI Ultraviolet

		Merrifield/Moorefield MID devices

		Goldfish (mostly Android emulator)



	  If you have one of these systems, or if you want to build a

	  generic distribution kernel, say Y here - otherwise say N.
@@ -667,6 +676,17 @@ config X86_INTEL_QUARK 
	  Say Y here if you have a Quark based system such as the Arduino

	  compatible Intel Galileo.



config X86_RDC321X

	bool "RDC R-321x SoC"

	depends on X86_32

	depends on X86_EXTENDED_PLATFORM

	select M486

	select X86_REBOOTFIXUPS

	help

	  This option is needed for RDC R-321x system-on-chip, also known

	  as R-8610-(G).

	  If you don't have one of these chips, you should say N here.



config X86_INTEL_LPSS

	bool "Intel Low Power Subsystem Support"

	depends on X86 && ACPI && PCI
@@ -720,17 +740,6 @@ config IOSF_MBI_DEBUG 


	  If you don't require the option or are in doubt, say N.



config X86_RDC321X

	bool "RDC R-321x SoC"

	depends on X86_32

	depends on X86_EXTENDED_PLATFORM

	select M486

	select X86_REBOOTFIXUPS

	help

	  This option is needed for RDC R-321x system-on-chip, also known

	  as R-8610-(G).

	  If you don't have one of these chips, you should say N here.



config X86_SUPPORTS_MEMORY_FAILURE

	def_bool y

	# MCE code calls memory_failure():
@@ -1565,7 +1574,6 @@ config ARCH_FLATMEM_ENABLE 


config ARCH_SPARSEMEM_ENABLE

	def_bool y

	depends on X86_64 || NUMA || X86_32

	select SPARSEMEM_STATIC if X86_32

	select SPARSEMEM_VMEMMAP_ENABLE if X86_64
@@ -2212,7 +2220,7 @@ config HOTPLUG_CPU 


config COMPAT_VDSO

	def_bool n

	prompt "Disable the 32-bit vDSO (needed for glibc 2.3.3)"

	prompt "Workaround for glibc 2.3.2 / 2.3.3 (released in year 2003/2004)"

	depends on COMPAT_32

	help

	  Certain buggy versions of glibc will crash if they are
@@ -2901,6 +2909,19 @@ config PCI_MMCONFIG 
	default y

	depends on PCI && (ACPI || JAILHOUSE_GUEST)

	depends on X86_64 || (PCI_GOANY || PCI_GOMMCONFIG)

	help

	  Add support for accessing the PCI configuration space as a memory

	  mapped area. It is the recommended method if the system supports

	  this (it must have PCI Express and ACPI for it to be available).



	  In the unlikely case that enabling this configuration option causes

	  problems, the mechanism can be switched off with the 'pci=nommconf'

	  command line parameter.



	  Say N only if you are sure that your platform does not support this

	  access method or you have problems caused by it.



	  Say Y otherwise.



config PCI_OLPC

	def_bool y
@@ -2915,13 +2936,21 @@ config MMCONF_FAM10H 
	depends on X86_64 && PCI_MMCONFIG && ACPI



config PCI_CNB20LE_QUIRK

	bool "Read CNB20LE Host Bridge Windows" if EXPERT

	depends on PCI

	bool "Read PCI host bridge windows from the CNB20LE chipset" if EXPERT

	depends on X86_32 && PCI

	help

	  Read the PCI windows out of the CNB20LE host bridge. This allows

	  PCI hotplug to work on systems with the CNB20LE chipset which do

	  not have ACPI.



	  The ServerWorks (later Broadcom) CNB20LE was a chipset designed

	  most probably only for Pentium III.



	  To find out if you have such a chipset, search for a PCI device with

	  1166:0009 PCI IDs, for example by executing

		lspci -nn | grep '1166:0009'

	  The code is inactive if there is none.



	  There's no public spec for this chipset, and this functionality

	  is known to be incomplete.

arch/x86/entry/calling.h

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,8 @@ For 32-bit we have the following conventions - kernel is built with 
	pushq	%rsi		/* pt_regs->si */

	movq	8(%rsp), %rsi	/* temporarily store the return address in %rsi */

	movq	%rdi, 8(%rsp)	/* pt_regs->di (overwriting original return address) */

	/* We just clobbered the return address - use the IRET frame for unwinding: */

	UNWIND_HINT_IRET_REGS offset=3*8

	.else

	pushq   %rdi		/* pt_regs->di */

	pushq   %rsi		/* pt_regs->si */

arch/x86/include/asm/nospec-branch.h

+0 −4
Original line number Diff line number Diff line
@@ -435,12 +435,8 @@ static inline void call_depth_return_thunk(void) {} 
 * Inline asm uses the %V modifier which is only in newer GCC

 * which is ensured when CONFIG_MITIGATION_RETPOLINE is defined.

 */

#ifdef CONFIG_MITIGATION_RETPOLINE

#define CALL_NOSPEC	__CS_PREFIX("%V[thunk_target]")	\

			"call __x86_indirect_thunk_%V[thunk_target]\n"

#else

#define CALL_NOSPEC	"call *%[thunk_target]\n"

#endif



# define THUNK_TARGET(addr) [thunk_target] "r" (addr)

arch/x86/kernel/cpu/microcode/amd.c

+1 −1
Original line number Diff line number Diff line
@@ -600,7 +600,7 @@ static bool __apply_microcode_amd(struct microcode_amd *mc, u32 *cur_rev, 
	unsigned long p_addr = (unsigned long)&mc->hdr.data_code;



	if (!verify_sha256_digest(mc->hdr.patch_id, *cur_rev, (const u8 *)p_addr, psize))

		return -1;

		return false;



	native_wrmsrl(MSR_AMD64_PATCH_LOADER, p_addr);