Commit 74bbd87d authored by Matthew Brost's avatar Matthew Brost
Browse files

drm/xe: Avoid unconditional VRAM reads in H2G path 



desc_read() issues an VRAM read which serializes the CPU and drains
posted writes on dGPU platforms. The H2G tracepoint evaluated its
arguments unconditionally, so even with tracing disabled the submission
path paid the full VRAM readf latency. Guard the tracepoint with
trace_xe_guc_ctb_h2g_enabled().

Adso move the descriptor status verification under CONFIG_DRM_XE_DEBUG.
This removes another unnecessary VRAM read in non-debug builfds.

This results in ~10× faster H2G submission and significantly reduces
lock contention across the driver.

Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarStuart Summers <stuart.summers@intel.com>
Reviewed-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
Link: https://patch.msgid.link/20260218043319.809548-3-matthew.brost@intel.com
parent af3de6cf

drivers/gpu/drm/xe/xe_guc_ct.c

+16 −9
Original line number Diff line number Diff line
@@ -939,23 +939,23 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len, 
	u32 full_len;

	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,

							 tail * sizeof(u32));

	u32 desc_status;



	full_len = len + GUC_CTB_HDR_LEN;



	lockdep_assert_held(&ct->lock);

	xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);



	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {

		u32 desc_tail = desc_read(xe, h2g, tail);

		u32 desc_head = desc_read(xe, h2g, head);

		u32 desc_status;



		desc_status = desc_read(xe, h2g, status);

		if (desc_status) {

			xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);

			goto corrupted;

		}



	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {

		u32 desc_tail = desc_read(xe, h2g, tail);

		u32 desc_head = desc_read(xe, h2g, head);



		if (tail != desc_tail) {

			desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);

			xe_gt_err(gt, "CT write: tail was modified %u != %u\n", desc_tail, tail);
@@ -1023,6 +1023,13 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len, 
	/* Update descriptor */

	desc_write(xe, h2g, tail, h2g->info.tail);



	/*

	 * desc_read() performs an VRAM read which serializes the CPU and drains

	 * posted writes on dGPU platforms. Tracepoints evaluate arguments even

	 * when disabled, so guard the event to avoid adding µs-scale latency to

	 * the fast H2G submission path when tracing is not active.

	 */

	if (trace_xe_guc_ctb_h2g_enabled())

		trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1), full_len,

				     desc_read(xe, h2g, head), h2g->info.tail);