Unverified Commit 7554729d authored by Alex Elder's avatar Alex Elder Committed by Yixun Lan
Browse files

clk: spacemit: mark K1 pll1_d8 as critical 



The pll1_d8 clock is enabled by the boot loader, and is ultimately a
parent for numerous clocks, including those used by APB and AXI buses.
Guodong Xu discovered that this clock got disabled while responding to
getting -EPROBE_DEFER when requesting a reset controller.

The needed clock (CLK_DMA, along with its parents) had already been
enabled.  To respond to the probe deferral return, the CLK_DMA clock
was disabled, and this led to parent clocks also reducing their enable
count.  When the enable count for pll1_d8 was decremented it became 0,
which caused it to be disabled.  This led to a system hang.

Marking that clock critical resolves this by preventing it from being
disabled.

Define a new macro CCU_FACTOR_GATE_DEFINE() to allow clock flags to
be supplied for a CCU_FACTOR_GATE clock.

Fixes: 1b72c59d ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Signed-off-by: default avatarAlex Elder <elder@riscstar.com>
Tested-by: default avatarGuodong Xu <guodong@riscstar.com>
Reviewed-by: default avatarHaylen Chu <heylenay@4d2.org>
Link: https://lore.kernel.org/r/20250612224856.1105924-1-elder@riscstar.com


Signed-off-by: default avatarYixun Lan <dlan@gentoo.org>
parent 19272b37

drivers/clk/spacemit/ccu-k1.c

+2 −1
Original line number Diff line number Diff line
@@ -170,7 +170,8 @@ CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 
CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);

CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);

CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);

CCU_FACTOR_GATE_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1);

CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,

		CLK_IS_CRITICAL);

CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1);

CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1);

CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1);

drivers/clk/spacemit/ccu_mix.h

+8 −3
Original line number Diff line number Diff line
@@ -101,17 +101,22 @@ static struct ccu_mix _name = { \ 
	}									\

}



#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div,	\

			       _mul)						\

#define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div,	\

			       _mul, _flags)					\

static struct ccu_mix _name = {							\

	.gate	= CCU_GATE_INIT(_mask_gate),					\

	.factor	= CCU_FACTOR_INIT(_div, _mul),					\

	.common = {								\

		.reg_ctrl	= _reg_ctrl,					\

		CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, 0)	\

		CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, _flags)	\

	}									\

}



#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div,	\

			       _mul)						\

	CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div,	\

			       _mul, 0)



#define CCU_MUX_GATE_DEFINE(_name, _parents, _reg_ctrl, _shift, _width,		\

			    _mask_gate, _flags)					\

static struct ccu_mix _name = {							\