Commit 7560349e authored by Jianhua Lin's avatar Jianhua Lin Committed by Hans Verkuil
Browse files

media: mediatek: jpeg: support 34bits 



The HW iommu is able to support a 34-bit iova address-space (16GB),
enable this feature for the encoder/decoder driver by shifting the
address by two bits and setting the extended address registers.

Signed-off-by: default avatarJianhua Lin <jianhua.lin@mediatek.com>
Reviewed-by: default avatarNicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: default avatarNicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil@xs4all.nl>
parent 11beb0fc

drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c

+4 −1
Original line number Diff line number Diff line
@@ -1026,6 +1026,7 @@ static void mtk_jpeg_dec_device_run(void *priv) 
	spin_lock_irqsave(&jpeg->hw_lock, flags);

	mtk_jpeg_dec_reset(jpeg->reg_base);

	mtk_jpeg_dec_set_config(jpeg->reg_base,

				jpeg->variant->support_34bit,

				&jpeg_src_buf->dec_param,

				jpeg_src_buf->bs_size,

				&bs,
@@ -1570,7 +1571,8 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg) 
	src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);

	dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);



	result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base);

	result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base,

						 jpeg->variant->support_34bit);

	vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);



	buf_state = VB2_BUF_STATE_DONE;
@@ -1770,6 +1772,7 @@ static void mtk_jpegdec_worker(struct work_struct *work) 
	ctx->total_frame_num++;

	mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);

	mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,

				jpeg->variant->support_34bit,

				&jpeg_src_buf->dec_param,

				jpeg_src_buf->bs_size,

				&bs,

drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h

+4 −0
Original line number Diff line number Diff line
@@ -34,6 +34,8 @@ 


#define MTK_JPEG_MAX_EXIF_SIZE	(64 * 1024)



#define MTK_JPEG_ADDR_MASK GENMASK(1, 0)



/**

 * enum mtk_jpeg_ctx_state - states of the context state machine

 * @MTK_JPEG_INIT:		current state is initialized
@@ -62,6 +64,7 @@ enum mtk_jpeg_ctx_state { 
 * @cap_q_default_fourcc:	capture queue default fourcc

 * @multi_core:		mark jpeg hw is multi_core or not

 * @jpeg_worker:		jpeg dec or enc worker

 * @support_34bit:	flag to check support for 34-bit DMA address

 */

struct mtk_jpeg_variant {

	struct clk_bulk_data *clks;
@@ -78,6 +81,7 @@ struct mtk_jpeg_variant { 
	u32 cap_q_default_fourcc;

	bool multi_core;

	void (*jpeg_worker)(struct work_struct *work);

	bool support_34bit;

};



struct mtk_jpeg_src_buf {

drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c

+54 −19
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 
 *         Rick Chang <rick.chang@mediatek.com>

 */



#include <linux/bitfield.h>

#include <linux/bits.h>

#include <linux/clk.h>

#include <linux/interrupt.h>

#include <linux/irq.h>
@@ -279,23 +281,43 @@ static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, 
	writel(val, base + JPGDEC_REG_BRZ_FACTOR);

}



static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y,

				       u32 addr_u, u32 addr_v)

static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, bool support_34bit,

				       dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)

{

	u32 val;



	mtk_jpeg_verify_align(addr_y, 16, JPGDEC_REG_DEST_ADDR0_Y);

	writel(addr_y, base + JPGDEC_REG_DEST_ADDR0_Y);

	writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR0_Y);

	mtk_jpeg_verify_align(addr_u, 16, JPGDEC_REG_DEST_ADDR0_U);

	writel(addr_u, base + JPGDEC_REG_DEST_ADDR0_U);

	writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR0_U);

	mtk_jpeg_verify_align(addr_v, 16, JPGDEC_REG_DEST_ADDR0_V);

	writel(addr_v, base + JPGDEC_REG_DEST_ADDR0_V);

	writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR0_V);

	if (support_34bit) {

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));

		writel(val, base + JPGDEC_REG_DEST_ADDR0_Y_EXT);

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));

		writel(val, base + JPGDEC_REG_DEST_ADDR0_U_EXT);

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));

		writel(val, base + JPGDEC_REG_DEST_ADDR0_V_EXT);

	}

}



static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y,

				       u32 addr_u, u32 addr_v)

static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, bool support_34bit,

				       dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)

{

	writel(addr_y, base + JPGDEC_REG_DEST_ADDR1_Y);

	writel(addr_u, base + JPGDEC_REG_DEST_ADDR1_U);

	writel(addr_v, base + JPGDEC_REG_DEST_ADDR1_V);

	u32 val;



	writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR1_Y);

	writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR1_U);

	writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR1_V);

	if (support_34bit) {

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));

		writel(val, base + JPGDEC_REG_DEST_ADDR1_Y_EXT);

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));

		writel(val, base + JPGDEC_REG_DEST_ADDR1_U_EXT);

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));

		writel(val, base + JPGDEC_REG_DEST_ADDR1_V_EXT);

	}

}



static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y,
@@ -322,18 +344,30 @@ static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode) 
	writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE);

}



static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr)

static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, bool support_34bit, dma_addr_t ptr)

{

	u32 val;



	mtk_jpeg_verify_align(ptr, 16, JPGDEC_REG_FILE_BRP);

	writel(ptr, base + JPGDEC_REG_FILE_BRP);

	writel(lower_32_bits(ptr), base + JPGDEC_REG_FILE_BRP);

	if (support_34bit) {

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(ptr));

		writel(val, base + JPGDEC_REG_FILE_BRP_EXT);

	}

}



static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size,

				     u32 bitstream_size)

static void mtk_jpeg_dec_set_bs_info(void __iomem *base, bool support_34bit,

				     dma_addr_t addr, u32 size, u32 bitstream_size)

{

	u32 val;



	mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);

	mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);

	writel(addr, base + JPGDEC_REG_FILE_ADDR);

	writel(lower_32_bits(addr), base + JPGDEC_REG_FILE_ADDR);

	if (support_34bit) {

		val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr));

		writel(val, base + JPGDEC_REG_FILE_ADDR_EXT);

	}

	writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);

	writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);

}
@@ -404,6 +438,7 @@ static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num, 
}



void mtk_jpeg_dec_set_config(void __iomem *base,

			     bool support_34bits,

			     struct mtk_jpeg_dec_param *cfg,

			     u32 bitstream_size,

			     struct mtk_jpeg_bs *bs,
@@ -413,8 +448,8 @@ void mtk_jpeg_dec_set_config(void __iomem *base, 
	mtk_jpeg_dec_set_dec_mode(base, 0);

	mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);

	mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);

	mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size, bitstream_size);

	mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr);

	mtk_jpeg_dec_set_bs_info(base, support_34bits, bs->str_addr, bs->size, bitstream_size);

	mtk_jpeg_dec_set_bs_write_ptr(base, support_34bits, bs->end_addr);

	mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,

				       (cfg->comp_num == 1) ? 1 : 0);

	mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
@@ -432,9 +467,9 @@ void mtk_jpeg_dec_set_config(void __iomem *base, 
				    cfg->mem_stride[1]);

	mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],

				    cfg->img_stride[1]);

	mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0],

	mtk_jpeg_dec_set_dst_bank0(base, support_34bits, fb->plane_addr[0],

				   fb->plane_addr[1], fb->plane_addr[2]);

	mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0);

	mtk_jpeg_dec_set_dst_bank1(base, support_34bits, 0, 0, 0);

	mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,

				   cfg->dma_last_mcu);

	mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);

drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param); 
u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base);

u32 mtk_jpeg_dec_enum_result(u32 irq_result);

void mtk_jpeg_dec_set_config(void __iomem *base,

			     bool support_34bits,

			     struct mtk_jpeg_dec_param *cfg,

			     u32 bitstream_size,

			     struct mtk_jpeg_bs *bs,

drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -46,5 +46,13 @@ 
#define JPGDEC_REG_INTERRUPT_STATUS	0x0274

#define JPGDEC_REG_STATUS		0x0278

#define JPGDEC_REG_BIT_STREAM_SIZE	0x0344

#define JPGDEC_REG_DEST_ADDR0_Y_EXT	0x0360

#define JPGDEC_REG_DEST_ADDR0_U_EXT	0x0364

#define JPGDEC_REG_DEST_ADDR0_V_EXT	0x0368

#define JPGDEC_REG_DEST_ADDR1_Y_EXT	0x036c

#define JPGDEC_REG_DEST_ADDR1_U_EXT	0x0370

#define JPGDEC_REG_DEST_ADDR1_V_EXT	0x0374

#define JPGDEC_REG_FILE_ADDR_EXT	0x0378

#define JPGDEC_REG_FILE_BRP_EXT		0x037c



#endif /* _MTK_JPEG_REG_H */