Unverified Commit 759426c7 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Arnd Bergmann
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riscv: dts: thead: set dma-noncoherent to soc bus 



riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.

Signed-off-by: default avatarJisheng Zhang <jszhang@kernel.org>
Tested-by: default avatarDrew Fustini <dfustini@baylibre.com>
Reviewed-by: default avatarGuo Ren <guoren@kernel.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent e4078ebb

arch/riscv/boot/dts/thead/th1520.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ soc { 
		interrupt-parent = <&plic>;

		#address-cells = <2>;

		#size-cells = <2>;

		dma-noncoherent;

		ranges;



		plic: interrupt-controller@ffd8000000 {