Commit 761d527d authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 

Cross-merge networking fixes after downstream PR.

No conflicts.

Adjacent changes:

drivers/net/ethernet/broadcom/bnxt/bnxt.h
  c948c097 ("bnxt_en: Don't clear ntuple filters and rss contexts during ethtool ops")
  f2878cde ("bnxt_en: Add support to call FW to update a VNIC")

Link: https://patch.msgid.link/20240822210125.1542769-1-kuba@kernel.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents bfc52dee aa0743a2

Documentation/ABI/testing/sysfs-devices-system-cpu

+2 −1
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@@ -562,7 +562,8 @@ Description: Control Symmetric Multi Threading (SMT) 
			 ================ =========================================



			 If control status is "forceoff" or "notsupported" writes

			 are rejected.

			 are rejected. Note that enabling SMT on PowerPC skips

			 offline cores.



What:		/sys/devices/system/cpu/cpuX/power/energy_perf_bias

Date:		March 2019

Documentation/admin-guide/device-mapper/dm-crypt.rst

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@@ -162,6 +162,7 @@ iv_large_sectors 




Module parameters::



   max_read_size

   max_write_size

      Maximum size of read or write requests. When a request larger than this size

Documentation/arch/riscv/hwprobe.rst

+22 −14
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@@ -239,25 +239,33 @@ The following keys are defined: 
       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned

    accesses is unknown.

* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing

  the performance of misaligned scalar native word accesses on the selected set

  of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are

    emulated via software, either in or below the kernel.  These accesses are

    always extremely slow.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of

    misaligned scalar accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower

    than equivalent byte accesses.  Misaligned accesses may be supported

    directly in hardware, or trapped and emulated by software.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar

    accesses are emulated via software, either in or below the kernel.  These

    accesses are always extremely slow.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster

    than equivalent byte accesses.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native

    word sized accesses are slower than the equivalent quantity of byte

    accesses. Misaligned accesses may be supported directly in hardware, or

    trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are

    not supported at all and will generate a misaligned address fault.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native

    word sized accesses are faster than the equivalent quantity of byte

    accesses.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar

    accesses are not supported at all and will generate a misaligned address

    fault.



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicboz block in bytes.

Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Display Clock & Reset Controller on SM6350



maintainers:

  - Konrad Dybcio <konrad.dybcio@somainline.org>

  - Konrad Dybcio <konradybcio@kernel.org>



description: |

  Qualcomm display clock control module provides the clocks, resets and power

Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Global Clock & Reset Controller on MSM8994



maintainers:

  - Konrad Dybcio <konrad.dybcio@somainline.org>

  - Konrad Dybcio <konradybcio@kernel.org>



description: |

  Qualcomm global clock control module provides the clocks, resets and power