Commit 76255024 authored by Gary Bisson's avatar Gary Bisson Committed by Chun-Kuang Hu
Browse files

drm/mediatek: mtk_dsi: enable hs clock during pre-enable 



Some bridges, such as the TI SN65DSI83, require the HS clock to be
running in order to lock its PLL during its own pre-enable function.

Without this change, the bridge gives the following error:
sn65dsi83 14-002c: failed to lock PLL, ret=-110
sn65dsi83 14-002c: Unexpected link status 0x01
sn65dsi83 14-002c: reset the pipe

Move the necessary functions from enable to pre-enable.

Signed-off-by: default avatarGary Bisson <bisson.gary@gmail.com>
Reviewed-by: default avatarCK Hu <ck.hu@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # Chromebooks
Tested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com/


Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent 6de23f81

drivers/gpu/drm/mediatek/mtk_dsi.c

+17 −18
Original line number Diff line number Diff line
@@ -673,6 +673,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) 
	}

}



static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)

{

	if (!dsi->lanes_ready) {

		dsi->lanes_ready = true;

		mtk_dsi_rxtx_control(dsi);

		usleep_range(30, 100);

		mtk_dsi_reset_dphy(dsi);

		mtk_dsi_clk_ulp_mode_leave(dsi);

		mtk_dsi_lane0_ulp_mode_leave(dsi);

		mtk_dsi_clk_hs_mode(dsi, 0);

		usleep_range(1000, 3000);

		/* The reaction time after pulling up the mipi signal for dsi_rx */

	}

}



static int mtk_dsi_poweron(struct mtk_dsi *dsi)

{

	struct device *dev = dsi->host.dev;
@@ -725,6 +740,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) 
	mtk_dsi_set_vm_cmd(dsi);

	mtk_dsi_config_vdo_timing(dsi);

	mtk_dsi_set_interrupt_enable(dsi);

	mtk_dsi_lane_ready(dsi);

	mtk_dsi_clk_hs_mode(dsi, 1);



	return 0;

err_disable_engine_clk:
@@ -770,30 +787,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) 
	dsi->lanes_ready = false;

}



static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)

{

	if (!dsi->lanes_ready) {

		dsi->lanes_ready = true;

		mtk_dsi_rxtx_control(dsi);

		usleep_range(30, 100);

		mtk_dsi_reset_dphy(dsi);

		mtk_dsi_clk_ulp_mode_leave(dsi);

		mtk_dsi_lane0_ulp_mode_leave(dsi);

		mtk_dsi_clk_hs_mode(dsi, 0);

		usleep_range(1000, 3000);

		/* The reaction time after pulling up the mipi signal for dsi_rx */

	}

}



static void mtk_output_dsi_enable(struct mtk_dsi *dsi)

{

	if (dsi->enabled)

		return;



	mtk_dsi_lane_ready(dsi);

	mtk_dsi_set_mode(dsi);

	mtk_dsi_clk_hs_mode(dsi, 1);



	mtk_dsi_start(dsi);



	dsi->enabled = true;