Commit 763d584c authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/cpufeature' into for-next/core 

* for-next/cpufeature:
  kselftest/arm64: Add 2024 dpISA extensions to hwcap test
  KVM: arm64: Allow control of dpISA extensions in ID_AA64ISAR3_EL1
  arm64/hwcap: Describe 2024 dpISA extensions to userspace
  arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-12
  arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented
  arm64/sme: Move storage of reg_smidr to __cpuinfo_store_cpu()
  arm64/sysreg: Update ID_AA64ISAR2_EL1 to DDI0601 2024-09
  arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601 2024-09
  arm64/sysreg: Update ID_AA64FPFR0_EL1 to DDI0601 2024-09
  arm64/sysreg: Update ID_AA64ISAR3_EL1 to DDI0601 2024-09
  arm64/sysreg: Update ID_AA64PFR2_EL1 to DDI0601 2024-09
  arm64/sysreg: Get rid of CPACR_ELx SysregFields
  arm64/sysreg: Convert *_EL12 accessors to Mapping
  arm64/sysreg: Get rid of the TCR2_EL1x SysregFields
  arm64/sysreg: Allow a 'Mapping' descriptor for system registers
  arm64/cpufeature: Refactor conditional logic in init_cpu_ftr_reg()
  arm64: cpufeature: Add HAFT to cpucap_is_possible()
parents f818fd30 8600640d

Documentation/arch/arm64/elf_hwcaps.rst

+76 −13
Original line number Diff line number Diff line
@@ -174,26 +174,82 @@ HWCAP_GCS 
    Functionality implied by ID_AA64PFR1_EL1.GCS == 0b1, as

    described by Documentation/arch/arm64/gcs.rst.



HWCAP_CMPBR

    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0010.



HWCAP_FPRCVT

    Functionality implied by ID_AA64ISAR3_EL1.FPRCVT == 0b0001.



HWCAP_F8MM8

    Functionality implied by ID_AA64FPFR0_EL1.F8MM8 == 0b0001.



HWCAP_F8MM4

    Functionality implied by ID_AA64FPFR0_EL1.F8MM4 == 0b0001.



HWCAP_SVE_F16MM

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.F16MM == 0b0001.



HWCAP_SVE_ELTPERM

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.ELTPERM == 0b0001.



HWCAP_SVE_AES2

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.AES == 0b0011.



HWCAP_SVE_BFSCALE

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.B16B16 == 0b0010.



HWCAP_SVE2P2

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SVEver == 0b0011.



HWCAP_SME2P2

    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0011.



HWCAP_SME_SBITPERM

    Functionality implied by ID_AA64SMFR0_EL1.SBitPerm == 0b1.



HWCAP_SME_AES

    Functionality implied by ID_AA64SMFR0_EL1.AES == 0b1.



HWCAP_SME_SFEXPA

    Functionality implied by ID_AA64SMFR0_EL1.SFEXPA == 0b1.



HWCAP_SME_STMOP

    Functionality implied by ID_AA64SMFR0_EL1.STMOP == 0b1.



HWCAP_SME_SMOP4

    Functionality implied by ID_AA64SMFR0_EL1.SMOP4 == 0b1.



HWCAP2_DCPODP

    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.



HWCAP2_SVE2

    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SVEver == 0b0001.



HWCAP2_SVEAES

    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.AES == 0b0001.



HWCAP2_SVEPMULL

    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.AES == 0b0010.



HWCAP2_SVEBITPERM

    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.BitPerm == 0b0001.



HWCAP2_SVESHA3

    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SHA3 == 0b0001.



HWCAP2_SVESM4

    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SM4 == 0b0001.



HWCAP2_FLAGM2

    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
@@ -202,16 +258,20 @@ HWCAP2_FRINT 
    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.



HWCAP2_SVEI8MM

    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.I8MM == 0b0001.



HWCAP2_SVEF32MM

    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.F32MM == 0b0001.



HWCAP2_SVEF64MM

    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.F64MM == 0b0001.



HWCAP2_SVEBF16

    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.BF16 == 0b0001.



HWCAP2_I8MM

    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
@@ -277,7 +337,8 @@ HWCAP2_EBF16 
    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.



HWCAP2_SVE_EBF16

    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.BF16 == 0b0010.



HWCAP2_CSSC

    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
@@ -286,7 +347,8 @@ HWCAP2_RPRFM 
    Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.



HWCAP2_SVE2P1

    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SVEver == 0b0010.



HWCAP2_SME2

    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
@@ -313,7 +375,8 @@ HWCAP2_HBC 
    Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.



HWCAP2_SVE_B16B16

    Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.B16B16 == 0b0001.



HWCAP2_LRCPC3

    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.

arch/arm64/include/asm/cpucaps.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ cpucap_is_possible(const unsigned int cap) 
		return IS_ENABLED(CONFIG_ARM64_POE);

	case ARM64_HAS_GCS:

		return IS_ENABLED(CONFIG_ARM64_GCS);

	case ARM64_HAFT:

		return IS_ENABLED(CONFIG_ARM64_HAFT);

	case ARM64_UNMAP_KERNEL_AT_EL0:

		return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0);

	case ARM64_WORKAROUND_843419:

arch/arm64/include/asm/cpufeature.h

+1 −2
Original line number Diff line number Diff line
@@ -852,8 +852,7 @@ static inline bool system_supports_gcs(void) 


static inline bool system_supports_haft(void)

{

	return IS_ENABLED(CONFIG_ARM64_HAFT) &&

		cpus_have_final_cap(ARM64_HAFT);

	return cpus_have_final_cap(ARM64_HAFT);

}



static __always_inline bool system_supports_mpam(void)

arch/arm64/include/asm/el2_setup.h

+3 −3
Original line number Diff line number Diff line
@@ -154,7 +154,7 @@ 
/* Coprocessor traps */

.macro __init_el2_cptr

	__check_hvhe .LnVHE_\@, x1

	mov	x0, #CPACR_ELx_FPEN

	mov	x0, #CPACR_EL1_FPEN

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_\@

.LnVHE_\@:
@@ -332,7 +332,7 @@ 


	// (h)VHE case

	mrs	x0, cpacr_el1			// Disable SVE traps

	orr	x0, x0, #CPACR_ELx_ZEN

	orr	x0, x0, #CPACR_EL1_ZEN

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_\@
@@ -353,7 +353,7 @@ 


	// (h)VHE case

	mrs	x0, cpacr_el1			// Disable SME traps

	orr	x0, x0, #CPACR_ELx_SMEN

	orr	x0, x0, #CPACR_EL1_SMEN

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_sme_\@

arch/arm64/include/asm/hwcap.h

+15 −0
Original line number Diff line number Diff line
@@ -93,6 +93,21 @@ 
#define KERNEL_HWCAP_PACA		__khwcap_feature(PACA)

#define KERNEL_HWCAP_PACG		__khwcap_feature(PACG)

#define KERNEL_HWCAP_GCS		__khwcap_feature(GCS)

#define KERNEL_HWCAP_CMPBR		__khwcap_feature(CMPBR)

#define KERNEL_HWCAP_FPRCVT		__khwcap_feature(FPRCVT)

#define KERNEL_HWCAP_F8MM8		__khwcap_feature(F8MM8)

#define KERNEL_HWCAP_F8MM4		__khwcap_feature(F8MM4)

#define KERNEL_HWCAP_SVE_F16MM		__khwcap_feature(SVE_F16MM)

#define KERNEL_HWCAP_SVE_ELTPERM	__khwcap_feature(SVE_ELTPERM)

#define KERNEL_HWCAP_SVE_AES2		__khwcap_feature(SVE_AES2)

#define KERNEL_HWCAP_SVE_BFSCALE	__khwcap_feature(SVE_BFSCALE)

#define KERNEL_HWCAP_SVE2P2		__khwcap_feature(SVE2P2)

#define KERNEL_HWCAP_SME2P2		__khwcap_feature(SME2P2)

#define KERNEL_HWCAP_SME_SBITPERM	__khwcap_feature(SME_SBITPERM)

#define KERNEL_HWCAP_SME_AES		__khwcap_feature(SME_AES)

#define KERNEL_HWCAP_SME_SFEXPA		__khwcap_feature(SME_SFEXPA)

#define KERNEL_HWCAP_SME_STMOP		__khwcap_feature(SME_STMOP)

#define KERNEL_HWCAP_SME_SMOP4		__khwcap_feature(SME_SMOP4)



#define __khwcap2_feature(x)		(const_ilog2(HWCAP2_ ## x) + 64)

#define KERNEL_HWCAP_DCPODP		__khwcap2_feature(DCPODP)