Commit 76f75212 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm)
Browse files

dt-bindings: interrupt-controller: Convert snps,archs-idu-intc to DT schema 

Convert the ARC-HS Interrupt Distribution Unit interrupt controller
binding to schema format. It's a straight-forward conversion of the
typical interrupt controller.

Link: https://lore.kernel.org/r/20250505144830.1292495-1-robh@kernel.org


Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent 66276d21

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt

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* ARC-HS Interrupt Distribution Unit



  This optional 2nd level interrupt controller can be used in SMP configurations

  for dynamic IRQ routing, load balancing of common/external IRQs towards core

  intc.



Properties:



- compatible: "snps,archs-idu-intc"

- interrupt-controller: This is an interrupt controller.

- #interrupt-cells: Must be <1> or <2>.



  Value of the first cell specifies the "common" IRQ from peripheral to IDU.

  Number N of the particular interrupt line of IDU corresponds to the line N+24

  of the core interrupt controller.



  The (optional) second cell specifies any of the following flags:

    - bits[3:0] trigger type and level flags

        1 = low-to-high edge triggered

        2 = NOT SUPPORTED (high-to-low edge triggered)

        4 = active high level-sensitive <<< DEFAULT

        8 = NOT SUPPORTED (active low level-sensitive)

  When no second cell is specified, the interrupt is assumed to be level

  sensitive.



  The interrupt controller is accessed via the special ARC AUX register

  interface, hence "reg" property is not specified.



Example:

	core_intc: core-interrupt-controller {

		compatible = "snps,archs-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

	};



	idu_intc: idu-interrupt-controller {

		compatible = "snps,archs-idu-intc";

		interrupt-controller;

		interrupt-parent = <&core_intc>;

		#interrupt-cells = <1>;

	};



	some_device: serial@c0fc1000 {

		interrupt-parent = <&idu_intc>;

		interrupts = <0>;	/* upstream idu IRQ #24 */

	};

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARC-HS Interrupt Distribution Unit



maintainers:

  - Vineet Gupta <vgupta@kernel.org>



description: >

  ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt

  controller which can be used in SMP configurations for dynamic IRQ routing,

  load balancing of common/external IRQs towards core intc.



  The interrupt controller is accessed via the special ARC AUX register

  interface, hence "reg" property is not specified.



properties:

  compatible:

    const: snps,archs-idu-intc



  interrupt-controller: true



  '#interrupt-cells':

    description: |

      Number of interrupt specifier cells:

        - 1: only a common IRQ is specified.

        - 2: a second cell encodes trigger type and level flags:

            1 = low-to-high edge triggered

            4 = active high level-sensitive (default)

    enum: [1, 2]



required:

  - compatible

  - interrupt-controller

  - '#interrupt-cells'



additionalProperties: false



examples:

  - |

    interrupt-controller {

        compatible = "snps,archs-idu-intc";

        interrupt-controller;

        #interrupt-cells = <1>;

    };