Commit 774c6f27 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.11-2024-07-27' of... 

Merge tag 'amd-drm-fixes-6.11-2024-07-27' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.11-2024-07-27:

amdgpu:
- SMU 14.x update
- Fix contiguous VRAM handling for IB parsing
- GFX 12 fix
- Regression fix for old APUs

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240728025407.2115881-1-alexander.deucher@amd.com
parents 8400291e d2860084

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+8 −8
Original line number Diff line number Diff line
@@ -1778,7 +1778,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
	struct ttm_operation_ctx ctx = { false, false };

	struct amdgpu_vm *vm = &fpriv->vm;

	struct amdgpu_bo_va_mapping *mapping;

	int r;

	int i, r;



	addr /= AMDGPU_GPU_PAGE_SIZE;
@@ -1793,13 +1793,13 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
	if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket)

		return -EINVAL;



	if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {

	(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;

	amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);

	for (i = 0; i < (*bo)->placement.num_placement; i++)

		(*bo)->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;

	r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);

	if (r)

		return r;

	}



	return amdgpu_ttm_alloc_gart(&(*bo)->tbo);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+3 −3
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev) 
	if (!amdgpu_mes_log_enable)

		return 0;



	r = amdgpu_bo_create_kernel(adev, AMDGPU_MES_LOG_BUFFER_SIZE, PAGE_SIZE,

	r = amdgpu_bo_create_kernel(adev, adev->mes.event_log_size, PAGE_SIZE,

				    AMDGPU_GEM_DOMAIN_GTT,

				    &adev->mes.event_log_gpu_obj,

				    &adev->mes.event_log_gpu_addr,
@@ -113,7 +113,7 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev) 
		return r;

	}



	memset(adev->mes.event_log_cpu_addr, 0, PAGE_SIZE);

	memset(adev->mes.event_log_cpu_addr, 0, adev->mes.event_log_size);



	return  0;
@@ -1573,7 +1573,7 @@ static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused) 
	uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr);



	seq_hex_dump(m, "", DUMP_PREFIX_OFFSET, 32, 4,

		     mem, AMDGPU_MES_LOG_BUFFER_SIZE, false);

		     mem, adev->mes.event_log_size, false);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+3 −3
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ enum amdgpu_mes_priority_level { 


#define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */

#define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */

#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 /* Maximu log buffer size for MES */



struct amdgpu_mes_funcs;
@@ -135,6 +134,7 @@ struct amdgpu_mes { 
	unsigned long			*doorbell_bitmap;



	/* MES event log buffer */

	uint32_t			event_log_size;

	struct amdgpu_bo	*event_log_gpu_obj;

	uint64_t			event_log_gpu_addr;

	void				*event_log_cpu_addr;

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+2 −0
Original line number Diff line number Diff line
@@ -1163,6 +1163,8 @@ static int mes_v11_0_sw_init(void *handle) 
	adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;

	adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;



	adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;



	r = amdgpu_mes_init(adev);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+6 −2
Original line number Diff line number Diff line
@@ -551,8 +551,10 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes) 
	mes_set_hw_res_pkt.oversubscription_timer = 50;

	mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;



	mes_set_hw_res_pkt.enable_mes_event_int_logging = 0;

	if (amdgpu_mes_log_enable) {

		mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;

		mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;

	}



	return mes_v12_0_submit_pkt_and_poll_completion(mes,

			&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
@@ -1237,6 +1239,8 @@ static int mes_v12_0_sw_init(void *handle) 
	adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;

	adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;



	adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;



	r = amdgpu_mes_init(adev);

	if (r)

		return r;