Commit 77fe8f19 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.8-2024-01-25' of... 

Merge tag 'amd-drm-fixes-6.8-2024-01-25' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.8-2024-01-25:

amdgpu:
- AC/DC power supply tracking fix
- Don't show invalid vram vendor data
- SMU 13.0.x fixes
- GART fix for umr on systems without VRAM
- GFX 10/11 UNORD_DISPATCH fixes
- IPS display fixes (required for S0ix on some platforms)
- Misc fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240125221503.5019-1-alexander.deucher@amd.com
parents 83cd3be8 c82eb25c

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

+8 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) 
	struct amdgpu_bo_param bp;

	dma_addr_t dma_addr;

	struct page *p;

	unsigned long x;

	int ret;



	if (adev->gart.bo != NULL)
@@ -130,6 +131,10 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) 
	if (!p)

		return -ENOMEM;



	/* assign pages to this device */

	for (x = 0; x < (1UL << order); x++)

		p[x].mapping = adev->mman.bdev.dev_mapping;



	/* If the hardware does not support UTCL2 snooping of the CPU caches

	 * then set_memory_wc() could be used as a workaround to mark the pages

	 * as write combine memory.
@@ -223,6 +228,7 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) 
	unsigned int order = get_order(adev->gart.table_size);

	struct sg_table *sg = adev->gart.bo->tbo.sg;

	struct page *p;

	unsigned long x;

	int ret;



	ret = amdgpu_bo_reserve(adev->gart.bo, false);
@@ -234,6 +240,8 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) 
	sg_free_table(sg);

	kfree(sg);

	p = virt_to_page(adev->gart.ptr);

	for (x = 0; x < (1UL << order); x++)

		p[x].mapping = NULL;

	__free_pages(p, order);



	adev->gart.ptr = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

+16 −1
Original line number Diff line number Diff line
@@ -221,8 +221,23 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = { 
	NULL

};



static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj,

					    struct attribute *attr, int i)

{

	struct device *dev = kobj_to_dev(kobj);

	struct drm_device *ddev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = drm_to_adev(ddev);



	if (attr == &dev_attr_mem_info_vram_vendor.attr &&

	    !adev->gmc.vram_vendor)

		return 0;



	return attr->mode;

}



const struct attribute_group amdgpu_vram_mgr_attr_group = {

	.attrs = amdgpu_vram_mgr_attributes

	.attrs = amdgpu_vram_mgr_attributes,

	.is_visible = amdgpu_vram_attrs_is_visible

};



/**

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+1 −1
Original line number Diff line number Diff line
@@ -6589,7 +6589,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 
#ifdef __BIG_ENDIAN

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

#endif

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

			    prop->allow_tunneling);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+1 −1
Original line number Diff line number Diff line
@@ -3846,7 +3846,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 
			    (order_base_2(prop->queue_size / 4) - 1));

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

			    prop->allow_tunneling);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+2 −1
Original line number Diff line number Diff line
@@ -1950,7 +1950,8 @@ static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 
	static const u32 regBIF_BIOS_SCRATCH_4 = 0x50;

	u32 vram_info;



	if (!amdgpu_sriov_vf(adev)) {

	/* Only for dGPU, vendor informaton is reliable */

	if (!amdgpu_sriov_vf(adev) && !(adev->flags & AMD_IS_APU)) {

		vram_info = RREG32(regBIF_BIOS_SCRATCH_4);

		adev->gmc.vram_vendor = vram_info & 0xF;

	}