Loading arch/s390/include/asm/spinlock.h +4 −3 Original line number Diff line number Diff line Loading @@ -82,9 +82,10 @@ static inline void arch_spin_unlock(arch_spinlock_t *lp) kcsan_release(); asm_inline volatile( ALTERNATIVE("nop", ".insn rre,0xb2fa0000,7,0", ALT_FACILITY(49)) /* NIAI 7 */ " sth %1,%0\n" : "=R" (((unsigned short *) &lp->lock)[1]) : "d" (0) : "cc", "memory"); " sth %[zero],%[lock]\n" : [lock] "=R" (((unsigned short *)&lp->lock)[1]) : [zero] "d" (0) : "cc", "memory"); } /* Loading arch/s390/lib/spinlock.c +5 −5 Original line number Diff line number Diff line Loading @@ -76,8 +76,8 @@ static inline int arch_load_niai4(int *lock) asm_inline volatile( ALTERNATIVE("nop", ".insn rre,0xb2fa0000,4,0", ALT_FACILITY(49)) /* NIAI 4 */ " l %0,%1\n" : "=d" (owner) : "Q" (*lock) : "memory"); " l %[owner],%[lock]\n" : [owner] "=d" (owner) : [lock] "Q" (*lock) : "memory"); return owner; } Loading @@ -87,9 +87,9 @@ static inline int arch_cmpxchg_niai8(int *lock, int old, int new) asm_inline volatile( ALTERNATIVE("nop", ".insn rre,0xb2fa0000,8,0", ALT_FACILITY(49)) /* NIAI 8 */ " cs %0,%3,%1\n" : "=d" (old), "=Q" (*lock) : "0" (old), "d" (new), "Q" (*lock) " cs %[old],%[new],%[lock]\n" : [old] "+d" (old), [lock] "+Q" (*lock) : [new] "d" (new) : "cc", "memory"); return expected == old; } Loading Loading
arch/s390/include/asm/spinlock.h +4 −3 Original line number Diff line number Diff line Loading @@ -82,9 +82,10 @@ static inline void arch_spin_unlock(arch_spinlock_t *lp) kcsan_release(); asm_inline volatile( ALTERNATIVE("nop", ".insn rre,0xb2fa0000,7,0", ALT_FACILITY(49)) /* NIAI 7 */ " sth %1,%0\n" : "=R" (((unsigned short *) &lp->lock)[1]) : "d" (0) : "cc", "memory"); " sth %[zero],%[lock]\n" : [lock] "=R" (((unsigned short *)&lp->lock)[1]) : [zero] "d" (0) : "cc", "memory"); } /* Loading
arch/s390/lib/spinlock.c +5 −5 Original line number Diff line number Diff line Loading @@ -76,8 +76,8 @@ static inline int arch_load_niai4(int *lock) asm_inline volatile( ALTERNATIVE("nop", ".insn rre,0xb2fa0000,4,0", ALT_FACILITY(49)) /* NIAI 4 */ " l %0,%1\n" : "=d" (owner) : "Q" (*lock) : "memory"); " l %[owner],%[lock]\n" : [owner] "=d" (owner) : [lock] "Q" (*lock) : "memory"); return owner; } Loading @@ -87,9 +87,9 @@ static inline int arch_cmpxchg_niai8(int *lock, int old, int new) asm_inline volatile( ALTERNATIVE("nop", ".insn rre,0xb2fa0000,8,0", ALT_FACILITY(49)) /* NIAI 8 */ " cs %0,%3,%1\n" : "=d" (old), "=Q" (*lock) : "0" (old), "d" (new), "Q" (*lock) " cs %[old],%[new],%[lock]\n" : [old] "+d" (old), [lock] "+Q" (*lock) : [new] "d" (new) : "cc", "memory"); return expected == old; } Loading