Commit 796928c6 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
Browse files

drm/nouveau/nvdec/tu102-: prepare for GSP-RM 



- (temporarily) disable if GSP-RM detected, will be added later
- provide empty class list for non-GSP paths
- split tu102- from gm107, they will provide host classes later
- fixup HW engine instance masks

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-28-skeggsb@gmail.com
parent a6f992a8

drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h

+1 −0
Original line number Diff line number Diff line
@@ -12,5 +12,6 @@ struct nvkm_nvdec { 
};



int gm107_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);

int tu102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);

int ga102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+10 −10
Original line number Diff line number Diff line
@@ -2426,7 +2426,7 @@ nv162_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, tu102_fifo_new },

	.gr       = { 0x00000001, tu102_gr_new },

	.nvdec    = { 0x00000001, gm107_nvdec_new },

	.nvdec    = { 0x00000001, tu102_nvdec_new },

	.nvenc    = { 0x00000001, gm107_nvenc_new },

	.sec2     = { 0x00000001, tu102_sec2_new },

};
@@ -2461,7 +2461,7 @@ nv164_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, tu102_fifo_new },

	.gr       = { 0x00000001, tu102_gr_new },

	.nvdec    = { 0x00000003, gm107_nvdec_new },

	.nvdec    = { 0x00000003, tu102_nvdec_new },

	.nvenc    = { 0x00000001, gm107_nvenc_new },

	.sec2     = { 0x00000001, tu102_sec2_new },

};
@@ -2496,7 +2496,7 @@ nv166_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, tu102_fifo_new },

	.gr       = { 0x00000001, tu102_gr_new },

	.nvdec    = { 0x00000007, gm107_nvdec_new },

	.nvdec    = { 0x00000007, tu102_nvdec_new },

	.nvenc    = { 0x00000001, gm107_nvenc_new },

	.sec2     = { 0x00000001, tu102_sec2_new },

};
@@ -2531,7 +2531,7 @@ nv167_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, tu102_fifo_new },

	.gr       = { 0x00000001, tu102_gr_new },

	.nvdec    = { 0x00000001, gm107_nvdec_new },

	.nvdec    = { 0x00000001, tu102_nvdec_new },

	.nvenc    = { 0x00000001, gm107_nvenc_new },

	.sec2     = { 0x00000001, tu102_sec2_new },

};
@@ -2566,7 +2566,7 @@ nv168_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, tu102_fifo_new },

	.gr       = { 0x00000001, tu102_gr_new },

	.nvdec    = { 0x00000001, gm107_nvdec_new },

	.nvdec    = { 0x00000001, tu102_nvdec_new },

	.nvenc    = { 0x00000001, gm107_nvenc_new },

	.sec2     = { 0x00000001, tu102_sec2_new },

};
@@ -2620,7 +2620,7 @@ nv172_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2650,7 +2650,7 @@ nv173_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2680,7 +2680,7 @@ nv174_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2710,7 +2710,7 @@ nv176_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2740,7 +2740,7 @@ nv177_chipset = { 
	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild

+1 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: MIT

nvkm-y += nvkm/engine/nvdec/base.o

nvkm-y += nvkm/engine/nvdec/gm107.o

nvkm-y += nvkm/engine/nvdec/tu102.o

nvkm-y += nvkm/engine/nvdec/ga102.o

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

+2 −1
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ nvkm_nvdec_dtor(struct nvkm_engine *engine) 
static const struct nvkm_engine_func

nvkm_nvdec = {

	.dtor = nvkm_nvdec_dtor,

	.sclass = { {} },

};



int
@@ -58,4 +59,4 @@ nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device, 


	return nvkm_falcon_ctor(nvdec->func->flcn, &nvdec->engine.subdev,

				nvdec->engine.subdev.name, addr, &nvdec->falcon);

};
 
}

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga102.c

+4 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
 */

#include "priv.h"



#include <subdev/gsp.h>

#include <subdev/mc.h>

#include <subdev/timer.h>
@@ -57,5 +58,8 @@ int 
ga102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,

		struct nvkm_nvdec **pnvdec)

{

	if (nvkm_gsp_rm(device->gsp))

		return -ENODEV;



	return nvkm_nvdec_new_(ga102_nvdec_fwif, device, type, inst, 0x848000, pnvdec);

}