Commit 7a7f6045 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/misc' into for-next/core 

* for-next/misc:
  arm64: simplify arch_static_branch/_jump function
  arm64: Add the arm64.no32bit_el0 command line option
  arm64: defer clearing DAIF.D
  arm64: assembler: update stale comment for disable_step_tsk
  arm64/sysreg: Update PIE permission encodings
  arm64: Add Neoverse-V2 part
  arm64: Remove unnecessary irqflags alternative.h include
parents d4ea881f 588de8c6

Documentation/admin-guide/kernel-parameters.txt

+3 −0
Original line number Diff line number Diff line
@@ -431,6 +431,9 @@ 
	arcrimi=	[HW,NET] ARCnet - "RIM I" (entirely mem-mapped) cards

			Format: <io>,<irq>,<nodeID>



	arm64.no32bit_el0 [ARM64] Unconditionally disable the execution of

			32 bit applications.



	arm64.nobti	[ARM64] Unconditionally disable Branch Target

			Identification support

arch/arm64/include/asm/assembler.h

+1 −5
Original line number Diff line number Diff line
@@ -50,16 +50,12 @@ 
	msr	daif, \flags

	.endm



	.macro	enable_dbg

	msr	daifclr, #8

	.endm



	.macro	disable_step_tsk, flgs, tmp

	tbz	\flgs, #TIF_SINGLESTEP, 9990f

	mrs	\tmp, mdscr_el1

	bic	\tmp, \tmp, #DBG_MDSCR_SS

	msr	mdscr_el1, \tmp

	isb	// Synchronise with enable_dbg

	isb	// Take effect before a subsequent clear of DAIF.D

9990:

	.endm

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49

#define ARM_CPU_PART_CORTEX_A78C	0xD4B

#define ARM_CPU_PART_NEOVERSE_V2	0xD4F



#define APM_CPU_PART_XGENE		0x000

#define APM_CPU_VAR_POTENZA		0x00
@@ -159,6 +160,7 @@ 
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)

#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

arch/arm64/include/asm/irqflags.h

+0 −1
Original line number Diff line number Diff line
@@ -5,7 +5,6 @@ 
#ifndef __ASM_IRQFLAGS_H

#define __ASM_IRQFLAGS_H



#include <asm/alternative.h>

#include <asm/barrier.h>

#include <asm/ptrace.h>

#include <asm/sysreg.h>

arch/arm64/include/asm/jump_label.h

+15 −13
Original line number Diff line number Diff line
@@ -15,17 +15,23 @@ 


#define JUMP_LABEL_NOP_SIZE		AARCH64_INSN_SIZE



#define JUMP_TABLE_ENTRY(key, label)			\

	".pushsection	__jump_table, \"aw\"\n\t"	\

	".align		3\n\t"				\

	".long		1b - ., %l["#label"] - .\n\t"	\

	".quad		%c0 - .\n\t"			\

	".popsection\n\t"				\

	:  :  "i"(key) :  : label



static __always_inline bool arch_static_branch(struct static_key * const key,

					       const bool branch)

{

	char *k = &((char *)key)[branch];



	asm goto(

		"1:	nop					\n\t"

		 "	.pushsection	__jump_table, \"aw\"	\n\t"

		 "	.align		3			\n\t"

		 "	.long		1b - ., %l[l_yes] - .	\n\t"

		 "	.quad		%c0 - .			\n\t"

		 "	.popsection				\n\t"

		 :  :  "i"(&((char *)key)[branch]) :  : l_yes);

		JUMP_TABLE_ENTRY(k, l_yes)

		);



	return false;

l_yes:
@@ -35,15 +41,11 @@ static __always_inline bool arch_static_branch(struct static_key * const key, 
static __always_inline bool arch_static_branch_jump(struct static_key * const key,

						    const bool branch)

{

	char *k = &((char *)key)[branch];

	asm goto(

		"1:	b		%l[l_yes]		\n\t"

		 "	.pushsection	__jump_table, \"aw\"	\n\t"

		 "	.align		3			\n\t"

		 "	.long		1b - ., %l[l_yes] - .	\n\t"

		 "	.quad		%c0 - .			\n\t"

		 "	.popsection				\n\t"

		 :  :  "i"(&((char *)key)[branch]) :  : l_yes);



		JUMP_TABLE_ENTRY(k, l_yes)

		);

	return false;

l_yes:

	return true;