Commit 7acc76a3 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/display: Add PHY_CMN1_CONTROL register definitions 



Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
sending.

Bspec: 68962
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-10-jouni.hogander@intel.com
parent 6ecb8e58

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -285,6 +285,9 @@ 
#define PHY_CX0_TX_CONTROL(tx, control)	(0x400 + ((tx) - 1) * 0x200 + (control))

#define   CONTROL2_DISABLE_SINGLE_TX	REG_BIT(6)



#define PHY_CMN1_CONTROL(tx, control)	(0x800 + ((tx) - 1) * 0x200 + (control))

#define   CONTROL0_MAC_TRANSMIT_LFPS	REG_BIT(1)



/* C20 Registers */

#define PHY_C20_WR_ADDRESS_L		0xC02

#define PHY_C20_WR_ADDRESS_H		0xC03