Commit 7c09e605 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-5.13-1' of... 

Merge tag 'sunxi-clk-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

"Our usual PR for the Allwinner SoCs, this time adding support for sigma-delta
modulation on the V3s Audio PLL, and fixing a kernel doc header."

* tag 'sunxi-clk-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi: Demote non-conformant kernel-doc headers
  clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll
parents a38fd874 dcc35457

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

+22 −11
Original line number Diff line number Diff line
@@ -40,18 +40,29 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", 
 * the base (2x, 4x and 8x), and one variable divider (the one true

 * pll audio).

 *

 * We don't have any need for the variable divider for now, so we just

 * hardcode it to match with the clock names

 * With sigma-delta modulation for fractional-N on the audio PLL,

 * we have to use specific dividers. This means the variable divider

 * can no longer be used, as the audio codec requests the exact clock

 * rates we support through this mechanism. So we now hard code the

 * variable divider to 1. This means the clock rates will no longer

 * match the clock names.

 */

#define SUN8I_V3S_PLL_AUDIO_REG	0x008



static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",

static struct ccu_sdm_setting pll_audio_sdm_table[] = {

	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },

	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },

};



static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",

				       "osc24M", 0x008,

				       8, 7,	/* N */

				       0, 5,	/* M */

				       pll_audio_sdm_table, BIT(24),

				       0x284, BIT(31),

				       BIT(31),	/* gate */

				       BIT(28),	/* lock */

				   0);

				       CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",

					"osc24M", 0x0010,
@@ -524,10 +535,10 @@ static struct ccu_common *sun8i_v3_ccu_clks[] = { 
	&mipi_csi_clk.common,

};



/* We hardcode the divider to 4 for now */

/* We hardcode the divider to 1 for SDM support */

static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",

			    clk_parent_pll_audio,

			    4, 1, CLK_SET_RATE_PARENT);

			    1, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",

			    clk_parent_pll_audio,

			    2, 1, CLK_SET_RATE_PARENT);

drivers/clk/sunxi/clk-sun6i-ar100.c

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 


#include "clk-factors.h"



/**

/*

 * sun6i_get_ar100_factors - Calculates factors p, m for AR100

 *

 * AR100 rate is calculated as follows

drivers/clk/sunxi/clk-sun9i-core.c

+4 −4
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
#include "clk-factors.h"





/**

/*

 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4

 * PLL4 rate is calculated as follows

 * rate = (parent_rate * n >> p) / (m + 1);
@@ -90,7 +90,7 @@ static void __init sun9i_a80_pll4_setup(struct device_node *node) 
CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);





/**

/*

 * sun9i_a80_get_gt_factors() - calculates m factor for GT

 * GT rate is calculated as follows

 * rate = parent_rate / (m + 1);
@@ -145,7 +145,7 @@ static void __init sun9i_a80_gt_setup(struct device_node *node) 
CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);





/**

/*

 * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2

 * AHB rate is calculated as follows

 * rate = parent_rate >> p;
@@ -225,7 +225,7 @@ static void __init sun9i_a80_apb0_setup(struct device_node *node) 
CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);





/**

/*

 * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1

 * APB1 rate is calculated as follows

 * rate = (parent_rate >> p) / (m + 1);

drivers/clk/sunxi/clk-usb.c

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
#include <linux/spinlock.h>





/**

/*

 * sunxi_usb_reset... - reset bits in usb clk registers handling

 */