Commit 7c1dffd4 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8250.dtsi: add display system nodes 



Add device tree nodes for mdss, mdp, dsi0/1.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201203142105.841666-2-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 221f0ef3

arch/arm64/boot/dts/qcom/sm8250.dtsi

+295 −7
Original line number Diff line number Diff line
@@ -4,10 +4,12 @@ 
 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,dispcc-sm8250.h>

#include <dt-bindings/clock/qcom,gcc-sm8250.h>

#include <dt-bindings/clock/qcom,gpucc-sm8250.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/interconnect/qcom,osm-l3.h>

#include <dt-bindings/interconnect/qcom,sm8250.h>

#include <dt-bindings/mailbox/qcom-ipcc.h>

#include <dt-bindings/power/qcom-aoss-qmp.h>

#include <dt-bindings/power/qcom-rpmpd.h>
@@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 { 
		};



		gpu: gpu@3d00000 {

			/*

			 * note: the amd,imageon compatible makes it possible

			 * to use the drm/msm driver without the display node,

			 * make sure to remove it when display node is added

			 */

			compatible = "qcom,adreno-650.2",

				     "qcom,adreno",

				     "amd,imageon";

				     "qcom,adreno";

			#stream-id-cells = <16>;



			reg = <0 0x03d00000 0 0x40000>;
@@ -1809,6 +1805,298 @@ usb_2_dwc3: dwc3@a800000 { 
			};

		};



		mdss: mdss@ae00000 {

			compatible = "qcom,sdm845-mdss";

			reg = <0 0x0ae00000 0 0x1000>;

			reg-names = "mdss";



			interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,

					<&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,

					<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;

			interconnect-names = "notused", "mdp0-mem", "mdp1-mem";



			power-domains = <&dispcc MDSS_GDSC>;



			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

				 <&gcc GCC_DISP_HF_AXI_CLK>,

				 <&gcc GCC_DISP_SF_AXI_CLK>,

				 <&dispcc DISP_CC_MDSS_MDP_CLK>;

			clock-names = "iface", "bus", "nrt_bus", "core";



			assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;

			assigned-clock-rates = <460000000>;



			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <1>;



			iommus = <&apps_smmu 0x820 0x402>;



			status = "disabled";



			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			mdss_mdp: mdp@ae01000 {

				compatible = "qcom,sdm845-dpu";

				reg = <0 0x0ae01000 0 0x8f000>,

				      <0 0x0aeb0000 0 0x2008>;

				reg-names = "mdp", "vbif";



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&gcc GCC_DISP_HF_AXI_CLK>,

					 <&dispcc DISP_CC_MDSS_MDP_CLK>,

					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				clock-names = "iface", "bus", "core", "vsync";



				assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,

						  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				assigned-clock-rates = <460000000>,

						       <19200000>;



				operating-points-v2 = <&mdp_opp_table>;

				power-domains = <&rpmhpd SM8250_MMCX>;



				interrupt-parent = <&mdss>;

				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						dpu_intf1_out: endpoint {

							remote-endpoint = <&dsi0_in>;

						};

					};



					port@1 {

						reg = <1>;

						dpu_intf2_out: endpoint {

							remote-endpoint = <&dsi1_in>;

						};

					};

				};



				mdp_opp_table: mdp-opp-table {

					compatible = "operating-points-v2";



					opp-200000000 {

						opp-hz = /bits/ 64 <200000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-300000000 {

						opp-hz = /bits/ 64 <300000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-345000000 {

						opp-hz = /bits/ 64 <345000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-460000000 {

						opp-hz = /bits/ 64 <460000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};

				};

			};



			dsi0: dsi@ae94000 {

				compatible = "qcom,mdss-dsi-ctrl";

				reg = <0 0x0ae94000 0 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;



				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,

					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,

					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					<&gcc GCC_DISP_HF_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";



				operating-points-v2 = <&dsi_opp_table>;

				power-domains = <&rpmhpd SM8250_MMCX>;



				phys = <&dsi0_phy>;

				phy-names = "dsi";



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						dsi0_in: endpoint {

							remote-endpoint = <&dpu_intf1_out>;

						};

					};



					port@1 {

						reg = <1>;

						dsi0_out: endpoint {

						};

					};

				};

			};



			dsi0_phy: dsi-phy@ae94400 {

				compatible = "qcom,dsi-phy-7nm";

				reg = <0 0x0ae94400 0 0x200>,

				      <0 0x0ae94600 0 0x280>,

				      <0 0x0ae94900 0 0x260>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				#clock-cells = <1>;

				#phy-cells = <0>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&rpmhcc RPMH_CXO_CLK>;

				clock-names = "iface", "ref";



				status = "disabled";

			};



			dsi1: dsi@ae96000 {

				compatible = "qcom,mdss-dsi-ctrl";

				reg = <0 0x0ae96000 0 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;



				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,

					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,

					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&gcc GCC_DISP_HF_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";



				operating-points-v2 = <&dsi_opp_table>;

				power-domains = <&rpmhpd SM8250_MMCX>;



				phys = <&dsi1_phy>;

				phy-names = "dsi";



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						dsi1_in: endpoint {

							remote-endpoint = <&dpu_intf2_out>;

						};

					};



					port@1 {

						reg = <1>;

						dsi1_out: endpoint {

						};

					};

				};

			};



			dsi1_phy: dsi-phy@ae96400 {

				compatible = "qcom,dsi-phy-7nm";

				reg = <0 0x0ae96400 0 0x200>,

				      <0 0x0ae96600 0 0x280>,

				      <0 0x0ae96900 0 0x260>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				#clock-cells = <1>;

				#phy-cells = <0>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&rpmhcc RPMH_CXO_CLK>;

				clock-names = "iface", "ref";



				status = "disabled";



				dsi_opp_table: dsi-opp-table {

					compatible = "operating-points-v2";



					opp-187500000 {

						opp-hz = /bits/ 64 <187500000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-300000000 {

						opp-hz = /bits/ 64 <300000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-358000000 {

						opp-hz = /bits/ 64 <358000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};

				};

			};

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,sm8250-dispcc";

			reg = <0 0x0af00000 0 0x20000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&dsi0_phy 0>,

				 <&dsi0_phy 1>,

				 <&dsi1_phy 0>,

				 <&dsi1_phy 1>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <&sleep_clk>;

			clock-names = "bi_tcxo",

				      "dsi0_phy_pll_out_byteclk",

				      "dsi0_phy_pll_out_dsiclk",

				      "dsi1_phy_pll_out_byteclk",

				      "dsi1_phy_pll_out_dsiclk",

				      "dp_link_clk_divsel_ten",

				      "dp_vco_divided_clk_src_mux",

				      "dptx1_phy_pll_link_clk",

				      "dptx1_phy_pll_vco_div_clk",

				      "dptx2_phy_pll_link_clk",

				      "dptx2_phy_pll_vco_div_clk",

				      "edp_phy_pll_link_clk",

				      "edp_phy_pll_vco_div_clk",

				      "sleep_clk";

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm8250-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;