Unverified Commit 7c2e86f7 authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Stephen Boyd
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clk: clocking-wizard: Fix output clock register offset for Versal platforms 



The output clock register offset used in clk_wzrd_register_output_clocks
was incorrectly referencing 0x3C instead of 0x38, which caused
misconfiguration of output dividers on Versal platforms.

Correcting the off-by-one error ensures proper configuration of output
clocks.

Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent e0a94c6b

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

+1 −1
Original line number Diff line number Diff line
@@ -1112,7 +1112,7 @@ static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs) 
						(dev,

						 clkout_name, clk_name, 0,

						 clk_wzrd->base,

						 (WZRD_CLK_CFG_REG(is_versal, 3) + i * 8),

						 (WZRD_CLK_CFG_REG(is_versal, 2) + i * 8),

						 WZRD_CLKOUT_DIVIDE_SHIFT,

						 WZRD_CLKOUT_DIVIDE_WIDTH,

						 CLK_DIVIDER_ONE_BASED |