Commit 7cc5997d authored by Yinghai Lu's avatar Yinghai Lu Committed by Jesse Barnes
Browse files

PCI: separate pci_setup_bridge to small functions 



This is a good cleanup in itself, and makes it easier to modify specific
resource types in later code.

Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
Acked-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent b0fc889c

drivers/pci/setup-bus.c

+50 −16
Original line number Diff line number Diff line
@@ -134,18 +134,12 @@ EXPORT_SYMBOL(pci_setup_cardbus); 
   config space writes, so it's quite possible that an I/O window of

   the bridge will have some undesirable address (e.g. 0) after the

   first write. Ditto 64-bit prefetchable MMIO.  */

static void pci_setup_bridge(struct pci_bus *bus)

static void pci_setup_bridge_io(struct pci_bus *bus)

{

	struct pci_dev *bridge = bus->self;

	struct resource *res;

	struct pci_bus_region region;

	u32 l, bu, lu, io_upper16;



	if (pci_is_enabled(bridge))

		return;



	dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",

		 bus->secondary, bus->subordinate);

	u32 l, io_upper16;



	/* Set up the top and bottom of the PCI I/O segment for this bus. */

	res = bus->resource[0];
@@ -158,8 +152,7 @@ static void pci_setup_bridge(struct pci_bus *bus) 
		/* Set up upper 16 bits of I/O base/limit. */

		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);

		dev_info(&bridge->dev, "  bridge window %pR\n", res);

	}

	else {

	} else {

		/* Clear upper 16 bits of I/O base/limit. */

		io_upper16 = 0;

		l = 0x00f0;
@@ -171,21 +164,35 @@ static void pci_setup_bridge(struct pci_bus *bus) 
	pci_write_config_dword(bridge, PCI_IO_BASE, l);

	/* Update upper 16 bits of I/O base/limit. */

	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);

}



static void pci_setup_bridge_mmio(struct pci_bus *bus)

{

	struct pci_dev *bridge = bus->self;

	struct resource *res;

	struct pci_bus_region region;

	u32 l;



	/* Set up the top and bottom of the PCI Memory segment

	   for this bus. */

	/* Set up the top and bottom of the PCI Memory segment for this bus. */

	res = bus->resource[1];

	pcibios_resource_to_bus(bridge, &region, res);

	if (res->flags & IORESOURCE_MEM) {

		l = (region.start >> 16) & 0xfff0;

		l |= region.end & 0xfff00000;

		dev_info(&bridge->dev, "  bridge window %pR\n", res);

	}

	else {

	} else {

		l = 0x0000fff0;

		dev_info(&bridge->dev, "  bridge window [mem disabled]\n");

	}

	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);

}



static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)

{

	struct pci_dev *bridge = bus->self;

	struct resource *res;

	struct pci_bus_region region;

	u32 l, bu, lu;



	/* Clear out the upper 32 bits of PREF limit.

	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
@@ -204,8 +211,7 @@ static void pci_setup_bridge(struct pci_bus *bus) 
			lu = upper_32_bits(region.end);

		}

		dev_info(&bridge->dev, "  bridge window %pR\n", res);

	}

	else {

	} else {

		l = 0x0000fff0;

		dev_info(&bridge->dev, "  bridge window [mem pref disabled]\n");

	}
@@ -214,10 +220,38 @@ static void pci_setup_bridge(struct pci_bus *bus) 
	/* Set the upper 32 bits of PREF base & limit. */

	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);

	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);

}



static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)

{

	struct pci_dev *bridge = bus->self;



	if (pci_is_enabled(bridge))

		return;



	dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",

		 bus->secondary, bus->subordinate);



	if (type & IORESOURCE_IO)

		pci_setup_bridge_io(bus);



	if (type & IORESOURCE_MEM)

		pci_setup_bridge_mmio(bus);



	if (type & IORESOURCE_PREFETCH)

		pci_setup_bridge_mmio_pref(bus);



	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);

}



static void pci_setup_bridge(struct pci_bus *bus)

{

	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |

				  IORESOURCE_PREFETCH;



	__pci_setup_bridge(bus, type);

}



/* Check whether the bridge supports optional I/O and

   prefetchable memory ranges. If not, the respective

   base/limit registers must be read-only and read as 0. */