Commit 7d06015d authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull pci updates from Bjorn Helgaas:
 "Enumeration:

   - Enable Configuration RRS SV, which makes device readiness visible,
     early instead of during child bus scanning (Bjorn Helgaas)

   - Log debug messages about reset methods being used (Bjorn Helgaas)

   - Avoid reset when it has been disabled via sysfs (Nishanth
     Aravamudan)

   - Add common pci-ep-bus.yaml schema for exporting several peripherals
     of a single PCI function via devicetree (Andrea della Porta)

   - Create DT nodes for PCI host bridges to enable loading device tree
     overlays to create platform devices for PCI devices that have
     several features that require multiple drivers (Herve Codina)

  Resource management:

   - Enlarge devres table[] to accommodate bridge windows, ROM, IOV
     BARs, etc., and validate BAR index in devres interfaces (Philipp
     Stanner)

   - Fix typo that repeatedly distributed resources to a bridge instead
     of iterating over subordinate bridges, which resulted in too little
     space to assign some BARs (Kai-Heng Feng)

   - Relax bridge window tail sizing for optional resources, e.g., IOV
     BARs, to avoid failures when removing and re-adding devices (Ilpo
     Järvinen)

   - Allow drivers to enable devices even if we haven't assigned
     optional IOV resources to them (Ilpo Järvinen)

   - Rework handling of optional resources (IOV BARs, ROMs) to reduce
     failures if we can't allocate them (Ilpo Järvinen)

   - Fix a NULL dereference in the SR-IOV VF creation error path (Shay
     Drory)

   - Fix s390 mmio_read/write syscalls, which didn't cause page faults
     in some cases, which broke vfio-pci lazy mapping on first access
     (Niklas Schnelle)

   - Add pdev->non_mappable_bars to replace CONFIG_VFIO_PCI_MMAP, which
     was disabled only for s390 (Niklas Schnelle)

   - Support mmap of PCI resources on s390 except for ISM devices
     (Niklas Schnelle)

  ASPM:

   - Delay pcie_link_state deallocation to avoid dangling pointers that
     cause invalid references during hot-unplug (Daniel Stodden)

  Power management:

   - Allow PCI bridges to go to D3Hot when suspending on all non-x86
     systems (Manivannan Sadhasivam)

  Power control:

   - Create pwrctrl devices in pci_scan_device() to make it more
     symmetric with pci_pwrctrl_unregister() and make pwrctrl devices
     for PCI bridges possible (Manivannan Sadhasivam)

   - Unregister pwrctrl devices in pci_destroy_dev() so DOE, ASPM, etc.
     can still access devices after pci_stop_dev() (Manivannan
     Sadhasivam)

   - If there's a pwrctrl device for a PCI device, skip scanning it
     because the pwrctrl core will rescan the bus after the device is
     powered on (Manivannan Sadhasivam)

   - Add a pwrctrl driver for PCI slots based on voltage regulators
     described via devicetree (Manivannan Sadhasivam)

  Bandwidth control:

   - Add set_pcie_speed.sh to TEST_PROGS to fix issue when executing the
     set_pcie_cooling_state.sh test case (Yi Lai)

   - Avoid a NULL pointer dereference when we run out of bus numbers to
     assign for a bridge secondary bus (Lukas Wunner)

  Hotplug:

   - Drop superfluous pci_hotplug_slot_list, try_module_get() calls, and
     NULL pointer checks (Lukas Wunner)

   - Drop shpchp module init/exit logging, replace shpchp dbg() with
     ctrl_dbg(), and remove unused dbg(), err(), info(), warn() wrappers
     (Ilpo Järvinen)

   - Drop 'shpchp_debug' module parameter in favor of standard dynamic
     debugging (Ilpo Järvinen)

   - Drop unused cpcihp .get_power(), .set_power() function pointers
     (Guilherme Giacomo Simoes)

   - Disable hotplug interrupts in portdrv only when pciehp is not
     enabled to avoid issuing two hotplug commands too close together
     (Feng Tang)

   - Skip pciehp 'device replaced' check if the device has been removed
     to address a deadlock when resuming after a device was removed
     during system sleep (Lukas Wunner)

   - Don't enable pciehp hotplug interupt when resuming in poll mode
     (Ilpo Järvinen)

  Virtualization:

   - Fix bugs in 'pci=config_acs=' kernel command line parameter (Tushar
     Dave)

  DOE:

   - Expose supported DOE features via sysfs (Alistair Francis)

   - Allow DOE support to be enabled even if CXL isn't enabled (Alistair
     Francis)

  Endpoint framework:

   - Convert PCI device data so pci-epf-test works correctly on
     big-endian endpoint systems (Niklas Cassel)

   - Add BAR_RESIZABLE type to endpoint framework and add DWC core
     support for EPF drivers to set BAR_RESIZABLE type and size (Niklas
     Cassel)

   - Fix pci-epf-test double free that causes an oops if the host
     reboots and PERST# deassertion restarts endpoint BAR allocation
     (Christian Bruel)

   - Fix endpoint BAR testing so tests can skip disabled BARs instead of
     reporting them as failures (Niklas Cassel)

   - Widen endpoint test BAR size variable to accommodate BARs larger
     than INT_MAX (Niklas Cassel)

   - Remove unused tools 'pci' build target left over after moving tests
     to tools/testing/selftests/pci_endpoint (Jianfeng Liu)

  Altera PCIe controller driver:

   - Add DT binding and driver support for Agilex family (P-Tile,
     F-Tile, R-Tile) (Matthew Gerlach and D M, Sharath Kumar)

  AMD MDB PCIe controller driver:

   - Add DT binding and driver for AMD MDB (Multimedia DMA Bridge)
     (Thippeswamy Havalige)

  Broadcom STB PCIe controller driver:

   - Add BCM2712 MSI-X DT binding and interrupt controller drivers and
     add softdep on irq_bcm2712_mip driver to ensure that it is loaded
     first (Stanimir Varbanov)

   - Expand inbound window map to 64GB so it can accommodate BCM2712
     (Stanimir Varbanov)

   - Add BCM2712 support and DT updates (Stanimir Varbanov)

   - Apply link speed restriction before bringing link up, not after
     (Jim Quinlan)

   - Update Max Link Speed in Link Capabilities via the internal
     writable register, not the read-only config register (Jim Quinlan)

   - Handle regulator_bulk_get() error to avoid panic when we call
     regulator_bulk_free() later (Jim Quinlan)

   - Disable regulators only when removing the bus immediately below a
     Root Port because we don't support regulators deeper in the
     hierarchy (Jim Quinlan)

   - Make const read-only arrays static (Colin Ian King)

  Cadence PCIe endpoint driver:

   - Correct MSG TLP generation so endpoints can generate INTx messages
     (Hans Zhang)

  Freescale i.MX6 PCIe controller driver:

   - Identify the second controller on i.MX8MQ based on devicetree
     'linux,pci-domain' instead of DBI 'reg' address (Richard Zhu)

   - Remove imx_pcie_cpu_addr_fixup() since dwc core can now derive the
     ATU input address (using parent_bus_offset) from devicetree (Frank
     Li)

  Freescale Layerscape PCIe controller driver:

   - Drop deprecated 'num-ib-windows' and 'num-ob-windows' and
     unnecessary 'status' from example (Krzysztof Kozlowski)

   - Correct the syscon_regmap_lookup_by_phandle_args("fsl,pcie-scfg")
     arg_count to fix probe failure on LS1043A (Ioana Ciornei)

  HiSilicon STB PCIe controller driver:

   - Call phy_exit() to clean up if histb_pcie_probe() fails (Christophe
     JAILLET)

  Intel Gateway PCIe controller driver:

   - Remove intel_pcie_cpu_addr() since dwc core can now derive the ATU
     input address (using parent_bus_offset) from devicetree (Frank Li)

  Intel VMD host bridge driver:

   - Convert vmd_dev.cfg_lock from spinlock_t to raw_spinlock_t so
     pci_ops.read() will never sleep, even on PREEMPT_RT where
     spinlock_t becomes a sleepable lock, to avoid calling a sleeping
     function from invalid context (Ryo Takakura)

  MediaTek PCIe Gen3 controller driver:

   - Remove leftover mac_reset assert for Airoha EN7581 SoC (Lorenzo
     Bianconi)

   - Add EN7581 PBUS controller 'mediatek,pbus-csr' DT property and
     program host bridge memory aperture to this syscon node (Lorenzo
     Bianconi)

  Qualcomm PCIe controller driver:

   - Add qcom,pcie-ipq5332 binding (Varadarajan Narayanan)

   - Add qcom i.MX8QM and i.MX8QXP/DXP optional DMA interrupt (Alexander
     Stein)

   - Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry
     Baryshkov)

   - Make DT iommu property required for SA8775P and prohibited for
     SDX55 (Dmitry Baryshkov)

   - Add DT IOMMU and DMA-related properties for Qualcomm SM8450 (Dmitry
     Baryshkov)

   - Add endpoint DT properties for SAR2130P and enable endpoint mode in
     driver (Dmitry Baryshkov)

   - Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as
     RESERVED (Manivannan Sadhasivam)

  Rockchip DesignWare PCIe controller driver:

   - Describe rk3568 and rk3588 BARs as Resizable, not Fixed (Niklas
     Cassel)

  Synopsys DesignWare PCIe controller driver:

   - Add debugfs-based Silicon Debug, Error Injection, Statistical
     Counter support for DWC (Shradha Todi)

   - Add debugfs property to expose LTSSM status of DWC PCIe link (Hans
     Zhang)

   - Add Rockchip support for DWC debugfs features (Niklas Cassel)

   - Add dw_pcie_parent_bus_offset() to look up the parent bus address
     of a specified 'reg' property and return the offset from the CPU
     physical address (Frank Li)

   - Use dw_pcie_parent_bus_offset() to derive CPU -> ATU addr offset
     via 'reg[config]' for host controllers and 'reg[addr_space]' for
     endpoint controllers (Frank Li)

   - Apply struct dw_pcie.parent_bus_offset in ATU users to remove use
     of .cpu_addr_fixup() when programming ATU (Frank Li)

  TI J721E PCIe driver:

   - Correct the 'link down' interrupt bit for J784S4 (Siddharth
     Vadapalli)

  TI Keystone PCIe controller driver:

   - Describe AM65x BARs 2 and 5 as Resizable (not Fixed) and reduce
     alignment requirement from 1MB to 64KB (Niklas Cassel)

  Xilinx Versal CPM PCIe controller driver:

   - Free IRQ domain in probe error path to avoid leaking it
     (Thippeswamy Havalige)

   - Add DT .compatible "xlnx,versal-cpm5nc-host" and driver support for
     Versal Net CPM5NC Root Port controller (Thippeswamy Havalige)

   - Add driver support for CPM5_HOST1 (Thippeswamy Havalige)

  Miscellaneous:

   - Convert fsl,mpc83xx-pcie binding to YAML (J. Neuschäfer)

   - Use for_each_available_child_of_node_scoped() to simplify apple,
     kirin, mediatek, mt7621, tegra drivers (Zhang Zekun)"

* tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (197 commits)
  PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args()
  PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4
  misc: pci_endpoint_test: Add support for PCITEST_IRQ_TYPE_AUTO
  PCI: endpoint: pci-epf-test: Expose supported IRQ types in CAPS register
  PCI: dw-rockchip: Endpoint mode cannot raise INTx interrupts
  PCI: endpoint: Add intx_capable to epc_features struct
  dt-bindings: PCI: Add common schema for devices accessible through PCI BARs
  PCI: intel-gw: Remove intel_pcie_cpu_addr()
  PCI: imx6: Remove imx_pcie_cpu_addr_fixup()
  PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup()
  PCI: dwc: ep: Ensure proper iteration over outbound map windows
  PCI: dwc: ep: Use devicetree 'reg[addr_space]' to derive CPU -> ATU addr offset
  PCI: dwc: ep: Consolidate devicetree handling in dw_pcie_ep_get_resources()
  PCI: dwc: ep: Call epc_create() early in dw_pcie_ep_init()
  PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offset
  PCI: dwc: Add dw_pcie_parent_bus_offset() checking and debug
  PCI: dwc: Add dw_pcie_parent_bus_offset()
  PCI/bwctrl: Fix NULL pointer dereference on bus number exhaustion
  PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variant
  PCI: brcmstb: Make const read-only arrays static
  ...
parents 0c86b424 dea14019
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What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/lane_detect
Date:		February 2025
Contact:	Shradha Todi <shradha.t@samsung.com>
Description:	(RW) Write the lane number to be checked for detection.	Read
		will return whether PHY indicates receiver detection on the
		selected lane. The default selected lane is Lane0.

What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/rx_valid
Date:		February 2025
Contact:	Shradha Todi <shradha.t@samsung.com>
Description:	(RW) Write the lane number to be checked as valid or invalid.
		Read will return the status of PIPE RXVALID signal of the
		selected lane. The default selected lane is Lane0.

What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
Date:		February 2025
Contact:	Shradha Todi <shradha.t@samsung.com>
Description:	The "rasdes_err_inj" is a directory which can be used to inject
		errors into the system. The possible errors that can be injected
		are:

		  1) tx_lcrc            - TLP LCRC error injection TX Path
		  2) b16_crc_dllp       - 16b CRC error injection of ACK/NAK DLLP
		  3) b16_crc_upd_fc     - 16b CRC error injection of Update-FC DLLP
		  4) tx_ecrc            - TLP ECRC error injection TX Path
		  5) fcrc_tlp           - TLP's FCRC error injection TX Path
		  6) parity_tsos        - Parity error of TSOS
		  7) parity_skpos       - Parity error on SKPOS
		  8) rx_lcrc            - LCRC error injection RX Path
		  9) rx_ecrc            - ECRC error injection RX Path
		  10) tlp_err_seq       - TLPs SEQ# error
		  11) ack_nak_dllp_seq  - DLLPS ACK/NAK SEQ# error
		  12) ack_nak_dllp      - ACK/NAK DLLPs transmission block
		  13) upd_fc_dllp       - UpdateFC DLLPs transmission block
		  14) nak_dllp          - Always transmission for NAK DLLP
		  15) inv_sync_hdr_sym  - Invert SYNC header
		  16) com_pad_ts1       - COM/PAD TS1 order set
		  17) com_pad_ts2       - COM/PAD TS2 order set
		  18) com_fts           - COM/FTS FTS order set
		  19) com_idl           - COM/IDL E-idle order set
		  20) end_edb           - END/EDB symbol
		  21) stp_sdp           - STP/SDP symbol
		  22) com_skp           - COM/SKP SKP order set
		  23) posted_tlp_hdr    - Posted TLP Header credit value control
		  24) non_post_tlp_hdr  - Non-Posted TLP Header credit value control
		  25) cmpl_tlp_hdr      - Completion TLP Header credit value control
		  26) posted_tlp_data   - Posted TLP Data credit value control
		  27) non_post_tlp_data - Non-Posted TLP Data credit value control
		  28) cmpl_tlp_data     - Completion TLP Data credit value control
		  29) duplicate_tlp     - Generates duplicate TLPs
		  30) nullified_tlp     - Generates Nullified TLPs

		(WO) Write to the attribute will prepare controller to inject
		the respective error in the next transmission of data.

		Parameter required to write will change in the following ways:

		- Errors 9 and 10 are sequence errors. The write command:

		    echo <count> <diff> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>

		    <count>
			    Number of errors to be injected
		    <diff>
			    The difference to add or subtract from natural
			    sequence number to generate sequence error.
			    Allowed range from -4095 to 4095

		- Errors 23 to 28 are credit value error insertions. The write
		  command:

		    echo <count> <diff> <vc> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>

		    <count>
			    Number of errors to be injected
		    <diff>
			    The difference to add or subtract from UpdateFC
			    credit value. Allowed range from -4095 to 4095
		    <vc>
			    Target VC number

		- All other errors. The write command:

		    echo <count> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>

		    <count>
			    Number of errors to be injected

What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_enable
Date:		February 2025
Contact:	Shradha Todi <shradha.t@samsung.com>
Description:	The "rasdes_event_counters" is the directory which can be used
		to collect statistical data about the number of times a certain
		event has occurred in the controller. The list of possible
		events are:

		1) EBUF Overflow
		2) EBUF Underrun
		3) Decode Error
		4) Running Disparity Error
		5) SKP OS Parity Error
		6) SYNC Header Error
		7) Rx Valid De-assertion
		8) CTL SKP OS Parity Error
		9) 1st Retimer Parity Error
		10) 2nd Retimer Parity Error
		11) Margin CRC and Parity Error
		12) Detect EI Infer
		13) Receiver Error
		14) RX Recovery Req
		15) N_FTS Timeout
		16) Framing Error
		17) Deskew Error
		18) Framing Error In L0
		19) Deskew Uncompleted Error
		20) Bad TLP
		21) LCRC Error
		22) Bad DLLP
		23) Replay Number Rollover
		24) Replay Timeout
		25) Rx Nak DLLP
		26) Tx Nak DLLP
		27) Retry TLP
		28) FC Timeout
		29) Poisoned TLP
		30) ECRC Error
		31) Unsupported Request
		32) Completer Abort
		33) Completion Timeout
		34) EBUF SKP Add
		35) EBUF SKP Del

		(RW) Write 1 to enable the event counter and write 0 to disable
		the event counter. Read will return whether the counter is
		currently enabled or disabled. Counter is disabled by default.

What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_value
Date:		February 2025
Contact:	Shradha Todi <shradha.t@samsung.com>
Description:	(RO) Read will return the current value of the event counter.
		To reset the counter, counter should be disabled first and then
		enabled back using the "counter_enable" attribute.

What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/lane_select
Date:		February 2025
Contact:	Shradha Todi <shradha.t@samsung.com>
Description:	(RW) Some lanes in the event list are lane specific events.
		These include events from 1 to 11, as well as, 34 and 35. Write
		the lane number for which you wish the counter to be enabled,
		disabled, or value dumped. Read will return the current
		selected lane number. Lane0 is selected by default.

What:		/sys/kernel/debug/dwc_pcie_<dev>/ltssm_status
Date:		February 2025
Contact:	Hans Zhang <18255117159@163.com>
Description:	(RO) Read will return the current PCIe LTSSM state in both
		string and raw value.
+29 −0
Original line number Diff line number Diff line
@@ -583,3 +583,32 @@ Description:
		enclosure-specific indications "specific0" to "specific7",
		hence the corresponding led class devices are unavailable if
		the DSM interface is used.

What:		/sys/bus/pci/devices/.../doe_features
Date:		March 2025
Contact:	Linux PCI developers <linux-pci@vger.kernel.org>
Description:
		This directory contains a list of the supported Data Object
		Exchange (DOE) features. The features are the file name.
		The contents of each file is the raw Vendor ID and data
		object feature values.

		The value comes from the device and specifies the vendor and
		data object type supported. The lower (RHS of the colon) is
		the data object type in hex. The upper (LHS of the colon)
		is the vendor ID.

		As all DOE devices must support the DOE discovery feature,
		if DOE is supported you will at least see the doe_discovery
		file, with this contents:

		  # cat doe_features/doe_discovery
		  0001:00

		If the device supports other features you will see other
		files as well. For example if CMA/SPDM and secure CMA/SPDM
		are supported the doe_features directory will look like
		this:

		  # ls doe_features
		  0001:01        0001:02        doe_discovery
+3 −4
Original line number Diff line number Diff line
@@ -57,11 +57,10 @@ by the PCI controller driver.
   The PCI controller driver can then create a new EPC device by invoking
   devm_pci_epc_create()/pci_epc_create().

* devm_pci_epc_destroy()/pci_epc_destroy()
* pci_epc_destroy()

   The PCI controller driver can destroy the EPC device created by either
   devm_pci_epc_create() or pci_epc_create() using devm_pci_epc_destroy() or
   pci_epc_destroy().
   The PCI controller driver can destroy the EPC device created by
   pci_epc_create() using pci_epc_destroy().

* pci_epc_linkup()

+60 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom bcm2712 MSI-X Interrupt Peripheral support

maintainers:
  - Stanimir Varbanov <svarbanov@suse.de>

description:
  This interrupt controller is used to provide interrupt vectors to the
  generic interrupt controller (GIC) on bcm2712. It will be used as
  external MSI-X controller for PCIe root complex.

allOf:
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#

properties:
  compatible:
    const: brcm,bcm2712-mip

  reg:
    items:
      - description: Base register address
      - description: PCIe message address

  "#msi-cells":
    const: 0

  brcm,msi-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Shift the allocated MSI's.

unevaluatedProperties: false

required:
  - compatible
  - reg
  - msi-controller
  - msi-ranges

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    axi {
        #address-cells = <2>;
        #size-cells = <2>;

        msi-controller@1000130000 {
            compatible = "brcm,bcm2712-mip";
            reg = <0x10 0x00130000 0x00 0xc0>,
                  <0xff 0xfffff000 0x00 0x1000>;
            msi-controller;
            #msi-cells = <0>;
            msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
        };
    };
+10 −0
Original line number Diff line number Diff line
@@ -12,9 +12,19 @@ maintainers:

properties:
  compatible:
    description: Each family of socfpga has its own implementation of the
      PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
      family of chips. The Stratix10 family of chips is supported by the
      altr,pcie-root-port-2.0. The Agilex family of chips has three,
      non-register compatible, variants of PCIe Hard IP referred to as the
      F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.

    enum:
      - altr,pcie-root-port-1.0
      - altr,pcie-root-port-2.0
      - altr,pcie-root-port-3.0-f-tile
      - altr,pcie-root-port-3.0-p-tile
      - altr,pcie-root-port-3.0-r-tile

  reg:
    items:
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