Commit 7dc363e6 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Update DCN10 resource 



Update DCN10 to use legacy fast update and ensure that the MPCC count is
the same as the pipe_count.

Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9c78dc95

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

+2 −0
Original line number Diff line number Diff line
@@ -569,6 +569,7 @@ static const struct dc_debug_options debug_defaults_diags = { 
		.disable_pplib_clock_request = true,

		.disable_pplib_wm_range = true,

		.underflow_assert_delay_us = 0xFFFFFFFF,

		.enable_legacy_fast_update = true,

};



static void dcn10_dpp_destroy(struct dpp **dpp)
@@ -1631,6 +1632,7 @@ static bool dcn10_resource_construct( 
	/* valid pipe num */

	pool->base.pipe_count = j;

	pool->base.timing_generator_count = j;

	pool->base.mpcc_count = j;



	/* within dml lib, it is hard code to 4. If ASIC pipe is fused,

	 * the value may be changed