Commit 7fc2adcd authored by Tomi Valkeinen's avatar Tomi Valkeinen Committed by Tomi Valkeinen
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drm/rcar-du: Add support for r8a779h0 



Add support for r8a779h0. It is very similar to r8a779g0, but has only
one output.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Tested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241217-rcar-gh-dsi-v5-7-e77421093c05@ideasonboard.com
parent c303814c

drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c

+18 −0
Original line number Diff line number Diff line
@@ -546,6 +546,23 @@ static const struct rcar_du_device_info rcar_du_r8a779g0_info = { 
	.dsi_clk_mask =  BIT(1) | BIT(0),

};



static const struct rcar_du_device_info rcar_du_r8a779h0_info = {

	.gen = 4,

	.features = RCAR_DU_FEATURE_CRTC_IRQ

		  | RCAR_DU_FEATURE_VSP1_SOURCE

		  | RCAR_DU_FEATURE_NO_BLENDING,

	.channels_mask = BIT(0),

	.routes = {

		/* R8A779H0 has one MIPI DSI output. */

		[RCAR_DU_OUTPUT_DSI0] = {

			.possible_crtcs = BIT(0),

			.port = 0,

		},

	},

	.num_rpf = 5,

	.dsi_clk_mask = BIT(0),

};



static const struct of_device_id rcar_du_of_table[] = {

	{ .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },

	{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
@@ -572,6 +589,7 @@ static const struct of_device_id rcar_du_of_table[] = { 
	{ .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },

	{ .compatible = "renesas,du-r8a779a0", .data = &rcar_du_r8a779a0_info },

	{ .compatible = "renesas,du-r8a779g0", .data = &rcar_du_r8a779g0_info },

	{ .compatible = "renesas,du-r8a779h0", .data = &rcar_du_r8a779h0_info },

	{ }

};

drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c

+3 −1
Original line number Diff line number Diff line
@@ -107,10 +107,12 @@ static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp) 
		 */

		rcrtc = rcdu->crtcs;

		num_crtcs = rcdu->num_crtcs;

	} else if (rcdu->info->gen >= 3 && rgrp->num_crtcs > 1) {

	} else if ((rcdu->info->gen == 3 && rgrp->num_crtcs > 1) ||

		   rcdu->info->gen == 4) {

		/*

		 * On Gen3 dot clocks are setup through per-group registers,

		 * only available when the group has two channels.

		 * On Gen4 the registers are there for single channel too.

		 */

		rcrtc = &rcdu->crtcs[rgrp->index * 2];

		num_crtcs = rgrp->num_crtcs;