Commit 7fd3fa00 authored by Balasubramani Vivekanandan's avatar Balasubramani Vivekanandan Committed by Lucas De Marchi
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drm/xe: Set mask bits for CCS_MODE register 



CCS_MODE register requires setting mask bits from Xe2+ platforms. Set
the mask bits unconditionally, as those bits are unused for older
platforms.

Signed-off-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: stable@vger.kernel.org # v6.11+
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241008073628.377433-2-balasubramani.vivekanandan@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 23ea2c75)
[ Fix conflict with mmio refactors ]
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 59b723cd

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -517,7 +517,7 @@ 
 *   [4-6]     RSVD

 *   [7]       Disabled

 */

#define CCS_MODE				XE_REG(0x14804)

#define CCS_MODE				XE_REG(0x14804, XE_REG_OPTION_MASKED)

#define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */

#define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */

#define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)

drivers/gpu/drm/xe/xe_gt_ccs_mode.c

+6 −0
Original line number Diff line number Diff line
@@ -68,6 +68,12 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) 
		}

	}



	/*

	 * Mask bits need to be set for the register. Though only Xe2+

	 * platforms require setting of mask bits, it won't harm for older

	 * platforms as these bits are unused there.

	 */

	mode |= CCS_MODE_CSLICE_0_3_MASK << 16;

	xe_mmio_write32(gt, CCS_MODE, mode);



	xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",