Commit 80213934 authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Danilo Krummrich
Browse files

gpu: nova-core: compute layout of the FRTS region 



FWSEC-FRTS is run with the desired address of the FRTS region as
parameter, which we need to compute depending on some hardware
parameters.

Do this in a `FbLayout` structure, that will be later extended to
describe more memory regions used to boot the GSP.

Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Link: https://lore.kernel.org/r/20250619-nova-frts-v6-20-ecf41ef99252@nvidia.com


[ In doc-comment of FbLayout s/bootup process/boot process/ - Danilo ]
Signed-off-by: default avatarDanilo Krummrich <dakr@kernel.org>
parent 47c4846e

drivers/gpu/nova-core/fb.rs

+70 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



use core::ops::Range;



use kernel::prelude::*;

use kernel::sizes::*;

use kernel::types::ARef;

use kernel::{dev_warn, device};



use crate::dma::DmaObject;

use crate::driver::Bar0;

use crate::gpu::Chipset;

use crate::regs;



mod hal;
@@ -65,3 +69,69 @@ pub(crate) fn unregister(&self, bar: &Bar0) { 
        }

    }

}



/// Layout of the GPU framebuffer memory.

///

/// Contains ranges of GPU memory reserved for a given purpose during the GSP boot process.

#[derive(Debug)]

#[expect(dead_code)]

pub(crate) struct FbLayout {

    pub(crate) fb: Range<u64>,

    pub(crate) vga_workspace: Range<u64>,

    pub(crate) frts: Range<u64>,

}



impl FbLayout {

    /// Computes the FB layout.

    pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Result<Self> {

        let hal = hal::fb_hal(chipset);



        let fb = {

            let fb_size = hal.vidmem_size(bar);



            0..fb_size

        };



        let vga_workspace = {

            let vga_base = {

                const NV_PRAMIN_SIZE: u64 = SZ_1M as u64;

                let base = fb.end - NV_PRAMIN_SIZE;



                if hal.supports_display(bar) {

                    match regs::NV_PDISP_VGA_WORKSPACE_BASE::read(bar).vga_workspace_addr() {

                        Some(addr) => {

                            if addr < base {

                                const VBIOS_WORKSPACE_SIZE: u64 = SZ_128K as u64;



                                // Point workspace address to end of framebuffer.

                                fb.end - VBIOS_WORKSPACE_SIZE

                            } else {

                                addr

                            }

                        }

                        None => base,

                    }

                } else {

                    base

                }

            };



            vga_base..fb.end

        };



        let frts = {

            const FRTS_DOWN_ALIGN: u64 = SZ_128K as u64;

            const FRTS_SIZE: u64 = SZ_1M as u64;

            // TODO: replace with `align_down` once it lands.

            let frts_base = (vga_workspace.start & !(FRTS_DOWN_ALIGN - 1)) - FRTS_SIZE;



            frts_base..frts_base + FRTS_SIZE

        };



        Ok(Self {

            fb,

            vga_workspace,

            frts,

        })

    }

}

drivers/gpu/nova-core/fb/hal.rs

+10 −2
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
use crate::gpu::Chipset;



mod ga100;

mod ga102;

mod tu102;



pub(crate) trait FbHal {
@@ -16,6 +17,12 @@ pub(crate) trait FbHal { 
    ///

    /// This might fail if the address is too large for the receiving register.

    fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result;



    /// Returns `true` is display is supported.

    fn supports_display(&self, bar: &Bar0) -> bool;



    /// Returns the VRAM size, in bytes.

    fn vidmem_size(&self, bar: &Bar0) -> u64;

}



/// Returns the HAL corresponding to `chipset`.
@@ -24,8 +31,9 @@ pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { 


    match chipset {

        TU102 | TU104 | TU106 | TU117 | TU116 => tu102::TU102_HAL,

        GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 => {

            ga100::GA100_HAL

        GA100 => ga100::GA100_HAL,

        GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 => {

            ga102::GA102_HAL

        }

    }

}

drivers/gpu/nova-core/fb/hal/ga100.rs

+12 −0
Original line number Diff line number Diff line
@@ -25,6 +25,10 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { 
        .write(bar);

}



pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {

    !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()

}



/// Shift applied to the sysmem address before it is written into

/// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`,

const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 = 40;
@@ -39,6 +43,14 @@ fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { 


        Ok(())

    }



    fn supports_display(&self, bar: &Bar0) -> bool {

        display_enabled_ga100(bar)

    }



    fn vidmem_size(&self, bar: &Bar0) -> u64 {

        super::tu102::vidmem_size_gp102(bar)

    }

}



const GA100: Ga100 = Ga100;

drivers/gpu/nova-core/fb/hal/ga102.rs

0 → 100644
+36 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



use kernel::prelude::*;



use crate::driver::Bar0;

use crate::fb::hal::FbHal;

use crate::regs;



fn vidmem_size_ga102(bar: &Bar0) -> u64 {

    regs::NV_USABLE_FB_SIZE_IN_MB::read(bar).usable_fb_size()

}



struct Ga102;



impl FbHal for Ga102 {

    fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {

        super::ga100::read_sysmem_flush_page_ga100(bar)

    }



    fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {

        super::ga100::write_sysmem_flush_page_ga100(bar, addr);



        Ok(())

    }



    fn supports_display(&self, bar: &Bar0) -> bool {

        super::ga100::display_enabled_ga100(bar)

    }



    fn vidmem_size(&self, bar: &Bar0) -> u64 {

        vidmem_size_ga102(bar)

    }

}



const GA102: Ga102 = Ga102;

pub(super) const GA102_HAL: &dyn FbHal = &GA102;

drivers/gpu/nova-core/fb/hal/tu102.rs

+16 −0
Original line number Diff line number Diff line
@@ -26,6 +26,14 @@ pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result { 
    }

}



pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {

    !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()

}



pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {

    regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::read(bar).usable_fb_size()

}



struct Tu102;



impl FbHal for Tu102 {
@@ -36,6 +44,14 @@ fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { 
    fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {

        write_sysmem_flush_page_gm107(bar, addr)

    }



    fn supports_display(&self, bar: &Bar0) -> bool {

        display_enabled_gm107(bar)

    }



    fn vidmem_size(&self, bar: &Bar0) -> u64 {

        vidmem_size_gp102(bar)

    }

}



const TU102: Tu102 = Tu102;