Commit 802379b8 authored by Hojin Nam's avatar Hojin Nam Committed by Will Deacon
Browse files

perf: CXL: fix CPMU filter value mask length 



CPMU filter value is described as 4B length in CXL r3.0 8.2.7.2.2.
However, it is used as 2B length in code and comments.

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarHojin Nam <hj96.nam@samsung.com>
Link: https://lore.kernel.org/r/20240216014522.32321-1-hj96.nam@samsung.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 28139262

drivers/perf/cxl_pmu.c

+5 −5
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ 
#define   CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK	GENMASK_ULL(63, 59)



#define CXL_PMU_FILTER_CFG_REG(n, f)	(0x400 + 4 * ((f) + (n) * 8))

#define   CXL_PMU_FILTER_CFG_VALUE_MSK			GENMASK(15, 0)

#define   CXL_PMU_FILTER_CFG_VALUE_MSK			GENMASK(31, 0)



#define CXL_PMU_COUNTER_REG(n)		(0xc00 + 8 * (n))
@@ -314,9 +314,9 @@ static bool cxl_pmu_config1_get_edge(struct perf_event *event) 
}



/*

 * CPMU specification allows for 8 filters, each with a 16 bit value...

 * So we need to find 8x16bits to store it in.

 * As the value used for disable is 0xffff, a separate enable switch

 * CPMU specification allows for 8 filters, each with a 32 bit value...

 * So we need to find 8x32bits to store it in.

 * As the value used for disable is 0xffff_ffff, a separate enable switch

 * is needed.

 */
@@ -642,7 +642,7 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags) 
		if (cxl_pmu_config1_hdm_filter_en(event))

			cfg = cxl_pmu_config2_get_hdm_decoder(event);

		else

			cfg = GENMASK(15, 0); /* No filtering if 0xFFFF_FFFF */

			cfg = GENMASK(31, 0); /* No filtering if 0xFFFF_FFFF */

		writeq(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0));

	}