Commit 80402804 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'loongarch-kvm-6.19' of... 

Merge tag 'loongarch-kvm-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD

LoongArch KVM changes for v6.19

1. Get VM PMU capability from HW GCFG register.
2. Add AVEC basic support.
3. Use 64-bit register definition for EIOINTC.
4. Add KVM timer test cases for tools/selftests.
parents 679fcce0 0f90fa6e

arch/loongarch/include/asm/kvm_eiointc.h

+8 −47
Original line number Diff line number Diff line
@@ -10,10 +10,7 @@ 


#define EIOINTC_IRQS			256

#define EIOINTC_ROUTE_MAX_VCPUS		256

#define EIOINTC_IRQS_U8_NUMS		(EIOINTC_IRQS / 8)

#define EIOINTC_IRQS_U16_NUMS		(EIOINTC_IRQS_U8_NUMS / 2)

#define EIOINTC_IRQS_U32_NUMS		(EIOINTC_IRQS_U8_NUMS / 4)

#define EIOINTC_IRQS_U64_NUMS		(EIOINTC_IRQS_U8_NUMS / 8)

#define EIOINTC_IRQS_U64_NUMS		(EIOINTC_IRQS / 64)

/* map to ipnum per 32 irqs */

#define EIOINTC_IRQS_NODETYPE_COUNT	16
@@ -64,54 +61,18 @@ struct loongarch_eiointc { 
	uint32_t status;



	/* hardware state */

	union nodetype {

		u64 reg_u64[EIOINTC_IRQS_NODETYPE_COUNT / 4];

		u32 reg_u32[EIOINTC_IRQS_NODETYPE_COUNT / 2];

		u16 reg_u16[EIOINTC_IRQS_NODETYPE_COUNT];

		u8 reg_u8[EIOINTC_IRQS_NODETYPE_COUNT * 2];

	} nodetype;

	u64 nodetype[EIOINTC_IRQS_NODETYPE_COUNT / 4];



	/* one bit shows the state of one irq */

	union bounce {

		u64 reg_u64[EIOINTC_IRQS_U64_NUMS];

		u32 reg_u32[EIOINTC_IRQS_U32_NUMS];

		u16 reg_u16[EIOINTC_IRQS_U16_NUMS];

		u8 reg_u8[EIOINTC_IRQS_U8_NUMS];

	} bounce;



	union isr {

		u64 reg_u64[EIOINTC_IRQS_U64_NUMS];

		u32 reg_u32[EIOINTC_IRQS_U32_NUMS];

		u16 reg_u16[EIOINTC_IRQS_U16_NUMS];

		u8 reg_u8[EIOINTC_IRQS_U8_NUMS];

	} isr;

	union coreisr {

		u64 reg_u64[EIOINTC_ROUTE_MAX_VCPUS][EIOINTC_IRQS_U64_NUMS];

		u32 reg_u32[EIOINTC_ROUTE_MAX_VCPUS][EIOINTC_IRQS_U32_NUMS];

		u16 reg_u16[EIOINTC_ROUTE_MAX_VCPUS][EIOINTC_IRQS_U16_NUMS];

		u8 reg_u8[EIOINTC_ROUTE_MAX_VCPUS][EIOINTC_IRQS_U8_NUMS];

	} coreisr;

	union enable {

		u64 reg_u64[EIOINTC_IRQS_U64_NUMS];

		u32 reg_u32[EIOINTC_IRQS_U32_NUMS];

		u16 reg_u16[EIOINTC_IRQS_U16_NUMS];

		u8 reg_u8[EIOINTC_IRQS_U8_NUMS];

	} enable;

	u64 bounce[EIOINTC_IRQS_U64_NUMS];

	u64 isr[EIOINTC_IRQS_U64_NUMS];

	u64 coreisr[EIOINTC_ROUTE_MAX_VCPUS][EIOINTC_IRQS_U64_NUMS];

	u64 enable[EIOINTC_IRQS_U64_NUMS];



	/* use one byte to config ipmap for 32 irqs at once */

	union ipmap {

		u64 reg_u64;

		u32 reg_u32[EIOINTC_IRQS_U32_NUMS / 4];

		u16 reg_u16[EIOINTC_IRQS_U16_NUMS / 4];

		u8 reg_u8[EIOINTC_IRQS_U8_NUMS / 4];

	} ipmap;

	u64 ipmap;

	/* use one byte to config coremap for one irq */

	union coremap {

		u64 reg_u64[EIOINTC_IRQS / 8];

		u32 reg_u32[EIOINTC_IRQS / 4];

		u16 reg_u16[EIOINTC_IRQS / 2];

		u8 reg_u8[EIOINTC_IRQS];

	} coremap;

	u64 coremap[EIOINTC_IRQS / 8];



	DECLARE_BITMAP(sw_coreisr[EIOINTC_ROUTE_MAX_VCPUS][LOONGSON_IP_NUM], EIOINTC_IRQS);

	uint8_t  sw_coremap[EIOINTC_IRQS];

arch/loongarch/include/asm/kvm_host.h

+8 −0
Original line number Diff line number Diff line
@@ -126,6 +126,8 @@ struct kvm_arch { 
	struct kvm_phyid_map  *phyid_map;

	/* Enabled PV features */

	unsigned long pv_features;

	/* Supported KVM features */

	unsigned long kvm_features;



	s64 time_offset;

	struct kvm_context __percpu *vmcs;
@@ -293,6 +295,12 @@ static inline int kvm_get_pmu_num(struct kvm_vcpu_arch *arch) 
	return (arch->cpucfg[6] & CPUCFG6_PMNUM) >> CPUCFG6_PMNUM_SHIFT;

}



/* Check whether KVM support this feature (VMM may disable it) */

static inline bool kvm_vm_support(struct kvm_arch *arch, int feature)

{

	return !!(arch->kvm_features & BIT_ULL(feature));

}



bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu);



/* Debug: dump vcpu state */

arch/loongarch/include/asm/kvm_vcpu.h

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#define CPU_PMU				(_ULCAST_(1) << 10)

#define CPU_TIMER			(_ULCAST_(1) << 11)

#define CPU_IPI				(_ULCAST_(1) << 12)

#define CPU_AVEC                        (_ULCAST_(1) << 14)



/* Controlled by 0x52 guest exception VIP aligned to estat bit 5~12 */

#define CPU_IP0				(_ULCAST_(1))

arch/loongarch/include/asm/loongarch.h

+2 −0
Original line number Diff line number Diff line
@@ -511,6 +511,8 @@ 
#define  CSR_GCFG_GPERF_SHIFT		24

#define  CSR_GCFG_GPERF_WIDTH		3

#define  CSR_GCFG_GPERF			(_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT)

#define  CSR_GCFG_GPMP_SHIFT		23

#define  CSR_GCFG_GPMP			(_ULCAST_(0x1) << CSR_GCFG_GPMP_SHIFT)

#define  CSR_GCFG_GCI_SHIFT		20

#define  CSR_GCFG_GCI_WIDTH		2

#define  CSR_GCFG_GCI			(_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT)

arch/loongarch/include/uapi/asm/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ struct kvm_fpu { 
#define  KVM_LOONGARCH_VM_FEAT_PV_IPI		6

#define  KVM_LOONGARCH_VM_FEAT_PV_STEALTIME	7

#define  KVM_LOONGARCH_VM_FEAT_PTW		8

#define  KVM_LOONGARCH_VM_FEAT_MSGINT		9



/* Device Control API on vcpu fd */

#define KVM_LOONGARCH_VCPU_CPUCFG	0