Commit 8053d2ff authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull generic phy updates from Vinod Koul:
 "New HW Support:
   - Support for Embedded DisplayPort and DisplayPort submodes and
     driver support on Qualcomm X1E80100 edp driver
   - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000
     and eusb2-repeater for SMB2360
   - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy
   - Mediatek XFI T-PHY support for mt7988
   - Rockchip usbdp combo phy driver

  Updates:
   - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for
     X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage
     swing tables
   - Freescale imx8m-pci pcie link-up updates
   - Rockchip rx-common-refclk-mode support
   - More platform remove callback returning void conversions"

* tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits)
  dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x
  dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema
  phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000
  dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY
  dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000
  phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p
  phy: samsung-ufs: ufs: exit on first reported error
  phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header
  phy: rockchip: fix CONFIG_TYPEC dependency
  phy: rockchip: usbdp: fix uninitialized variable
  phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode
  dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode
  phy: rockchip: add usbdp combo phy driver
  dt-bindings: phy: add rockchip usbdp combo phy document
  phy: add driver for MediaTek XFI T-PHY
  dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings
  phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void
  phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5
  MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101.
  ...
parents d4e034b4 960b3f02

Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8MP HDMI PHY



maintainers:

  - Lucas Stach <l.stach@pengutronix.de>



properties:

  compatible:

    enum:

      - fsl,imx8mp-hdmi-phy



  reg:

    maxItems: 1



  "#clock-cells":

    const: 0



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: apb

      - const: ref



  "#phy-cells":

    const: 0



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - "#clock-cells"

  - clocks

  - clock-names

  - "#phy-cells"

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mp-clock.h>

    #include <dt-bindings/power/imx8mp-power.h>



    phy@32fdff00 {

        compatible = "fsl,imx8mp-hdmi-phy";

        reg = <0x32fdff00 0x100>;

        clocks = <&clk IMX8MP_CLK_HDMI_APB>,

                 <&clk IMX8MP_CLK_HDMI_24M>;

        clock-names = "apb", "ref";

        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;

        #clock-cells = <0>;

        #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/mediatek,mt7988-xfi-tphy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek MT7988 XFI T-PHY



maintainers:

  - Daniel Golle <daniel@makrotopia.org>



description:

  The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes

  used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in

  MediaTek's 10G-capabale MT7988 SoC.

  In MediaTek's SDK sources, this unit is referred to as "pextp".



properties:

  compatible:

    const: mediatek,mt7988-xfi-tphy



  reg:

    maxItems: 1



  clocks:

    items:

      - description: XFI PHY clock

      - description: XFI register clock



  clock-names:

    items:

      - const: xfipll

      - const: topxtal



  resets:

    items:

      - description: Reset controller corresponding to the phy instance.



  mediatek,usxgmii-performance-errata:

    $ref: /schemas/types.yaml#/definitions/flag

    description:

      One instance of the T-PHY on MT7988 suffers from a performance

      problem in 10GBase-R mode which needs a work-around in the driver.

      This flag enables a work-around ajusting an analog phy setting and

      is required for XFI Port0 of the MT7988 SoC to be in compliance with

      the SFP specification.



  "#phy-cells":

    const: 0



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mediatek,mt7988-clk.h>

    soc {

      #address-cells = <2>;

      #size-cells = <2>;



      phy@11f20000 {

        compatible = "mediatek,mt7988-xfi-tphy";

        reg = <0 0x11f20000 0 0x10000>;

        clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,

                 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;

        clock-names = "xfipll", "topxtal";

        resets = <&watchdog 14>;

        mediatek,usxgmii-performance-errata;

        #phy-cells = <0>;

      };

    };



...

Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip USBDP Combo PHY with Samsung IP block



maintainers:

  - Frank Wang <frank.wang@rock-chips.com>

  - Zhang Yubing <yubing.zhang@rock-chips.com>



properties:

  compatible:

    enum:

      - rockchip,rk3588-usbdp-phy



  reg:

    maxItems: 1



  "#phy-cells":

    description: |

      Cell allows setting the type of the PHY. Possible values are:

      - PHY_TYPE_USB3

      - PHY_TYPE_DP

    const: 1



  clocks:

    maxItems: 4



  clock-names:

    items:

      - const: refclk

      - const: immortal

      - const: pclk

      - const: utmi



  resets:

    maxItems: 5



  reset-names:

    items:

      - const: init

      - const: cmn

      - const: lane

      - const: pcs_apb

      - const: pma_apb



  rockchip,dp-lane-mux:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    minItems: 2

    maxItems: 4

    items:

      maximum: 3

    description:

      An array of physical Type-C lanes indexes. Position of an entry

      determines the DisplayPort (DP) lane index, while the value of an entry

      indicates physical Type-C lane. The supported DP lanes number are 2 or 4.

      e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,

      3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy

      lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =

      <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C

      phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If

      DP lanes are mapped by DisplayPort Alt mode, this property is not needed.



  rockchip,u2phy-grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the 'usb2 phy general register files'.



  rockchip,usb-grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the 'usb general register files'.



  rockchip,usbdpphy-grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the 'usbdp phy general register files'.



  rockchip,vo-grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the 'video output general register files'.

      When select the DP lane mapping will request its phandle.



  sbu1-dc-gpios:

    description:

      GPIO connected to the SBU1 line of the USB-C connector via a big resistor

      (~100K) to apply a DC offset for signalling the connector orientation.

    maxItems: 1



  sbu2-dc-gpios:

    description:

      GPIO connected to the SBU2 line of the USB-C connector via a big resistor

      (~100K) to apply a DC offset for signalling the connector orientation.

    maxItems: 1



  orientation-switch:

    description: Flag the port as possible handler of orientation switching

    type: boolean



  mode-switch:

    description: Flag the port as possible handler of altmode switching

    type: boolean



  port:

    $ref: /schemas/graph.yaml#/properties/port

    description:

      A port node to link the PHY to a TypeC controller for the purpose of

      handling orientation switching.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/rockchip,rk3588-cru.h>

    #include <dt-bindings/reset/rockchip,rk3588-cru.h>



    usbdp_phy0: phy@fed80000 {

      compatible = "rockchip,rk3588-usbdp-phy";

      reg = <0xfed80000 0x10000>;

      #phy-cells = <1>;

      clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,

               <&cru CLK_USBDP_PHY0_IMMORTAL>,

               <&cru PCLK_USBDPPHY0>,

               <&u2phy0>;

      clock-names = "refclk", "immortal", "pclk", "utmi";

      resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,

               <&cru SRST_USBDP_COMBO_PHY0_CMN>,

               <&cru SRST_USBDP_COMBO_PHY0_LANE>,

               <&cru SRST_USBDP_COMBO_PHY0_PCS>,

               <&cru SRST_P_USBDPPHY0>;

      reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";

      rockchip,u2phy-grf = <&usb2phy0_grf>;

      rockchip,usb-grf = <&usb_grf>;

      rockchip,usbdpphy-grf = <&usbdpphy0_grf>;

      rockchip,vo-grf = <&vo0_grf>;

    };

Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml

+1 −0
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@@ -21,6 +21,7 @@ properties: 
      - qcom,sc8180x-edp-phy

      - qcom,sc8280xp-dp-phy

      - qcom,sc8280xp-edp-phy

      - qcom,x1e80100-dp-phy



  reg:

    items:

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

+24 −4
Original line number Diff line number Diff line
@@ -88,11 +88,11 @@ properties: 
          - description: offset of PCIe 4-lane configuration register

          - description: offset of configuration bit for this PHY



  "#clock-cells":

    const: 0

  "#clock-cells": true



  clock-output-names:

    maxItems: 1

    minItems: 1

    maxItems: 2



  "#phy-cells":

    const: 0
@@ -198,7 +198,6 @@ allOf: 
            enum:

              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

              - qcom,x1e80100-qmp-gen3x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x2-pcie-phy

    then:

      properties:
@@ -213,6 +212,27 @@ allOf: 
        reset-names:

          maxItems: 1



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm8450-qmp-gen4x2-pcie-phy

              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

    then:

      properties:

        clock-output-names:

          minItems: 2

        "#clock-cells":

          const: 1

    else:

      properties:

        clock-output-names:

          maxItems: 1

        "#clock-cells":

          const: 0



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>