Commit 807d90b5 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: support SDMA v3 struct fw front door load



Add support for new SDMA firmware struct (V3) with PSP
front door load type.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5251b56e
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+1 −0
Original line number Diff line number Diff line
@@ -2464,6 +2464,7 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
		*type = GFX_FW_TYPE_DMUB;
		break;
	case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
	case AMDGPU_UCODE_ID_SDMA_RS64:
		*type = GFX_FW_TYPE_SDMA_UCODE_TH0;
		break;
	case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
+10 −0
Original line number Diff line number Diff line
@@ -212,6 +212,7 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
	const struct common_firmware_header *header = NULL;
	int err, i;
	const struct sdma_firmware_header_v2_0 *sdma_hdr;
	const struct sdma_firmware_header_v3_0 *sdma_hv3;
	uint16_t version_major;
	char ucode_prefix[30];
	char fw_name[52];
@@ -287,6 +288,15 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
			adev->firmware.fw_size +=
				ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
			break;
		case 3:
			sdma_hv3 = (const struct sdma_firmware_header_v3_0 *)
				adev->sdma.instance[0].fw->data;
			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_RS64];
			info->ucode_id = AMDGPU_UCODE_ID_SDMA_RS64;
			info->fw = adev->sdma.instance[0].fw;
			adev->firmware.fw_size +=
				ALIGN(le32_to_cpu(sdma_hv3->ucode_size_bytes), PAGE_SIZE);
			break;
		default:
			err = -EINVAL;
		}
+7 −0
Original line number Diff line number Diff line
@@ -797,6 +797,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
	const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
	const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
	const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
	const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL;
	const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
	const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;
	const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL;
@@ -818,6 +819,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
	dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
	mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
	sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data;
	imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
	vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
	umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data;
@@ -834,6 +836,11 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
			ucode_addr = (u8 *)ucode->fw->data +
				le32_to_cpu(sdma_hdr->ctl_ucode_offset);
			break;
		case AMDGPU_UCODE_ID_SDMA_RS64:
			ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes);
			ucode_addr = (u8 *)ucode->fw->data +
				le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes);
			break;
		case AMDGPU_UCODE_ID_CP_MEC1:
		case AMDGPU_UCODE_ID_CP_MEC2:
			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
+1 −0
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@@ -464,6 +464,7 @@ enum AMDGPU_UCODE_ID {
	AMDGPU_UCODE_ID_SDMA7,
	AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
	AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
	AMDGPU_UCODE_ID_SDMA_RS64,
	AMDGPU_UCODE_ID_CP_CE,
	AMDGPU_UCODE_ID_CP_PFP,
	AMDGPU_UCODE_ID_CP_ME,