Commit 80834997 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Will Deacon
Browse files

arm64: el2_setup.h: Make __init_el2_fgt labels consistent, again 



Commit 5b39db60 ("arm64: el2_setup.h: Rename some labels to be more
diff-friendly") reworked the labels in __init_el2_fgt to say what's
skipped rather than what the target location is. The exception was
"set_fgt_" which is where registers are written. In reviewing the BRBE
additions, Will suggested "set_debug_fgt_" where HDFGxTR_EL2 are
written. Doing that would partially revert commit 5b39db60 undoing
the goal of minimizing additions here, but it would follow the
convention for labels where registers are written.

So let's do both. Branches that skip something go to a "skip" label and
places that set registers have a "set" label. This results in some
double labels, but it makes things entirely consistent.

While we're here, the SME skip label was incorrectly named, so fix it.

Reported-by: default avatarWill Deacon <will@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250520-arm-brbe-v19-v22-2-c1ddde38e7f8@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 694f574f

arch/arm64/include/asm/el2_setup.h

+7 −3
Original line number Diff line number Diff line
@@ -204,19 +204,21 @@ 
	orr	x0, x0, #(1 << 62)



.Lskip_spe_fgt_\@:



.Lset_debug_fgt_\@:

	msr_s	SYS_HDFGRTR_EL2, x0

	msr_s	SYS_HDFGWTR_EL2, x0



	mov	x0, xzr

	mrs	x1, id_aa64pfr1_el1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4

	cbz	x1, .Lskip_debug_fgt_\@

	cbz	x1, .Lskip_sme_fgt_\@



	/* Disable nVHE traps of TPIDR2 and SMPRI */

	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK



.Lskip_debug_fgt_\@:

.Lskip_sme_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1

	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4

	cbz	x1, .Lskip_pie_fgt_\@
@@ -237,12 +239,14 @@ 
	/* GCS depends on PIE so we don't check it if PIE is absent */

	mrs_s	x1, SYS_ID_AA64PFR1_EL1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4

	cbz	x1, .Lset_fgt_\@

	cbz	x1, .Lskip_gce_fgt_\@



	/* Disable traps of access to GCS registers at EL0 and EL1 */

	orr	x0, x0, #HFGxTR_EL2_nGCS_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nGCS_EL0_MASK



.Lskip_gce_fgt_\@:



.Lset_fgt_\@:

	msr_s	SYS_HFGRTR_EL2, x0

	msr_s	SYS_HFGWTR_EL2, x0