Commit 808b79eb authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF 



This power domain to disable DC states will be used in places outside
of DPLL, so making the name more generic.

Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarCaz Yokoyama <caz.yokoyama@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211020003558.222198-1-jose.souza@intel.com
parent ce679dea

drivers/gpu/drm/i915/display/intel_display_power.c

+3 −3
Original line number Diff line number Diff line
@@ -155,8 +155,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) 
		return "MODESET";

	case POWER_DOMAIN_GT_IRQ:

		return "GT_IRQ";

	case POWER_DOMAIN_DPLL_DC_OFF:

		return "DPLL_DC_OFF";

	case POWER_DOMAIN_DC_OFF:

		return "DC_OFF";

	case POWER_DOMAIN_TC_COLD_OFF:

		return "TC_COLD_OFF";

	default:
@@ -2803,7 +2803,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 
	ICL_PW_2_POWER_DOMAINS |			\

	BIT_ULL(POWER_DOMAIN_MODESET) |			\

	BIT_ULL(POWER_DOMAIN_AUX_A) |			\

	BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |			\

	BIT_ULL(POWER_DOMAIN_DC_OFF) |			\

	BIT_ULL(POWER_DOMAIN_INIT))



#define ICL_DDI_IO_A_POWER_DOMAINS (			\

drivers/gpu/drm/i915/display/intel_display_power.h

+1 −1
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_GMBUS,

	POWER_DOMAIN_MODESET,

	POWER_DOMAIN_GT_IRQ,

	POWER_DOMAIN_DPLL_DC_OFF,

	POWER_DOMAIN_DC_OFF,

	POWER_DOMAIN_TC_COLD_OFF,

	POWER_DOMAIN_INIT,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+3 −3
Original line number Diff line number Diff line
@@ -3741,7 +3741,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, 
		 * domain.

		 */

		pll->wakeref = intel_display_power_get(dev_priv,

						       POWER_DOMAIN_DPLL_DC_OFF);

						       POWER_DOMAIN_DC_OFF);

	}



	icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -3848,7 +3848,7 @@ static void combo_pll_disable(struct drm_i915_private *dev_priv, 


	if (IS_JSL_EHL(dev_priv) &&

	    pll->info->id == DPLL_ID_EHL_DPLL4)

		intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,

		intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,

					pll->wakeref);

}
@@ -4232,7 +4232,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915, 
	if (IS_JSL_EHL(i915) && pll->on &&

	    pll->info->id == DPLL_ID_EHL_DPLL4) {

		pll->wakeref = intel_display_power_get(i915,

						       POWER_DOMAIN_DPLL_DC_OFF);

						       POWER_DOMAIN_DC_OFF);

	}



	pll->state.pipe_mask = 0;