dt-bindings: display: imx: Add i.MX8qxp Display Controller (813f71ac) · Commits · git / linux-nf

Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc.yaml

0 → 100644

+236 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Freescale i.MX8qxp Display Controller

		description: \|
		The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
		components that include a blit engine for 2D graphics accelerations, display
		controller for display output processing, as well as a command sequencer.

		Display buffers Source buffers
		(AXI read master) (AXI read master)
		\| .......... \| \| \| \|
		+---------------------------+------------+------------------+-+-+------+
		\| Display Controller (DC) \| .......... \| \| \| \| \|
		\| \| \| \| \| \| \|
		\| @@@@@@@@@@@ +----------+------------+------------+ \| \| \| \|
		A \| \| Command \| \| V V \| \| \| \| \|
		X <-+->\| Sequencer \| \| @@@@@@@@@@@@@@@@@@@@@@@@@@@@ \| V V V \|
		I \| \| (AXI CLK) \| \| \| \| \| @@@@@@@@@@ \|
		\| @@@@@@@@@@@ \| \| Pixel Engine \| \| \| \| \|
		\| \| \| \| (AXI CLK) \| \| \| \| \|
		\| V \| @@@@@@@@@@@@@@@@@@@@@@@@@@@@ \| \| \| \|
		A \| *********** \| \| \| \| \| \| \| Blit \| \|
		H <-+->\| Configure \| \| V V V V \| \| Engine \| \|
		B \| \| (CFG CLK) \| \| 00000000000 11111111111 \| \| (AXI CLK)\| \|
		\| *********** \| \| Display \| \| Display \| \| \| \| \|
		\| \| \| Engine \| \| Engine \| \| \| \| \|
		\| \| \| (Disp CLK)\| \| (Disp CLK)\| \| \| \| \|
		\| @@@@@@@@@@@ \| 00000000000 11111111111 \| @@@@@@@@@@ \|
		I \| \| Common \| \| \| \| \| \| \|
		R <-+--\| Control \| \| \| Display \| \| \| \|
		Q \| \| (AXI CLK) \| \| \| Controller \| \| \| \|
		\| @@@@@@@@@@@ +------------------------------------+ \| \|
		\| \| \| ^ \| \|
		+--------------------------+----------------+-------+---------+--------+
		^ \| \| \| \|
		\| V V \| V
		Clocks & Resets Display Display Panic Destination
		Output0 Output1 Control buffer
		(AXI write master)

		maintainers:
		- Liu Ying <victor.liu@nxp.com>

		properties:
		compatible:
		const: fsl,imx8qxp-dc

		reg:
		maxItems: 1

		clocks:
		maxItems: 1

		resets:
		maxItems: 2

		reset-names:
		items:
		- const: axi
		- const: cfg

		power-domains:
		maxItems: 1

		"#address-cells":
		const: 1

		"#size-cells":
		const: 1

		ranges: true

		patternProperties:
		"^command-sequencer@[0-9a-f]+$":
		type: object
		additionalProperties: true

		properties:
		compatible:
		const: fsl,imx8qxp-dc-command-sequencer

		"^display-engine@[0-9a-f]+$":
		type: object
		additionalProperties: true

		properties:
		compatible:
		const: fsl,imx8qxp-dc-display-engine

		"^interrupt-controller@[0-9a-f]+$":
		type: object
		additionalProperties: true

		properties:
		compatible:
		const: fsl,imx8qxp-dc-intc

		"^pixel-engine@[0-9a-f]+$":
		type: object
		additionalProperties: true

		properties:
		compatible:
		const: fsl,imx8qxp-dc-pixel-engine

		"^pmu@[0-9a-f]+$":
		type: object
		additionalProperties: true

		properties:
		compatible:
		const: fsl,imx8qxp-dc-axi-performance-counter

		required:
		- compatible
		- reg
		- clocks
		- power-domains
		- "#address-cells"
		- "#size-cells"
		- ranges

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/imx8-lpcg.h>
		#include <dt-bindings/firmware/imx/rsrc.h>

		display-controller@56180000 {
		compatible = "fsl,imx8qxp-dc";
		reg = <0x56180000 0x40000>;
		clocks = <&dc0_lpcg IMX_LPCG_CLK_4>;
		power-domains = <&pd IMX_SC_R_DC_0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupt-controller@56180040 {
		compatible = "fsl,imx8qxp-dc-intc";
		reg = <0x56180040 0x60>;
		clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
		interrupt-controller;
		interrupt-parent = <&dc0_irqsteer>;
		#interrupt-cells = <1>;
		interrupts = <448>, <449>, <450>, <64>,
		<65>, <66>, <67>, <68>,
		<69>, <70>, <193>, <194>,
		<195>, <196>, <197>, <72>,
		<73>, <74>, <75>, <76>,
		<77>, <78>, <79>, <80>,
		<81>, <199>, <200>, <201>,
		<202>, <203>, <204>, <205>,
		<206>, <207>, <208>, <5>,
		<0>, <1>, <2>, <3>,
		<4>, <82>, <83>, <84>,
		<85>, <209>, <210>, <211>,
		<212>;
		interrupt-names = "store9_shdload",
		"store9_framecomplete",
		"store9_seqcomplete",
		"extdst0_shdload",
		"extdst0_framecomplete",
		"extdst0_seqcomplete",
		"extdst4_shdload",
		"extdst4_framecomplete",
		"extdst4_seqcomplete",
		"extdst1_shdload",
		"extdst1_framecomplete",
		"extdst1_seqcomplete",
		"extdst5_shdload",
		"extdst5_framecomplete",
		"extdst5_seqcomplete",
		"disengcfg_shdload0",
		"disengcfg_framecomplete0",
		"disengcfg_seqcomplete0",
		"framegen0_int0",
		"framegen0_int1",
		"framegen0_int2",
		"framegen0_int3",
		"sig0_shdload",
		"sig0_valid",
		"sig0_error",
		"disengcfg_shdload1",
		"disengcfg_framecomplete1",
		"disengcfg_seqcomplete1",
		"framegen1_int0",
		"framegen1_int1",
		"framegen1_int2",
		"framegen1_int3",
		"sig1_shdload",
		"sig1_valid",
		"sig1_error",
		"reserved",
		"cmdseq_error",
		"comctrl_sw0",
		"comctrl_sw1",
		"comctrl_sw2",
		"comctrl_sw3",
		"framegen0_primsync_on",
		"framegen0_primsync_off",
		"framegen0_secsync_on",
		"framegen0_secsync_off",
		"framegen1_primsync_on",
		"framegen1_primsync_off",
		"framegen1_secsync_on",
		"framegen1_secsync_off";
		};

		pixel-engine@56180800 {
		compatible = "fsl,imx8qxp-dc-pixel-engine";
		reg = <0x56180800 0xac00>;
		clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		};

		display-engine@5618b400 {
		compatible = "fsl,imx8qxp-dc-display-engine";
		reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
		reg-names = "top", "cfg";
		interrupt-parent = <&dc0_intc>;
		interrupts = <15>, <16>, <17>;
		interrupt-names = "shdload", "framecomplete", "seqcomplete";
		power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		};
		};