Commit 82367e7f authored by Roy Chan's avatar Roy Chan Committed by Alex Deucher
Browse files

drm/amd/display: fix missing writeback disablement if plane is removed 



[Why]
If the plane has been removed, the writeback disablement logic
doesn't run

[How]
fix the logic order

Acked-by: default avatarAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: default avatarRoy Chan <roy.chan@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f43a19fd

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+8 −6
Original line number Diff line number Diff line
@@ -1723,15 +1723,17 @@ void dcn20_program_front_end_for_ctx( 


				pipe = pipe->bottom_pipe;

			}

		}

		/* Program secondary blending tree and writeback pipes */

		pipe = &context->res_ctx.pipe_ctx[i];

			if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0

					&& (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)

		if (!pipe->top_pipe && !pipe->prev_odm_pipe

				&& pipe->stream && pipe->stream->num_wb_info > 0

				&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)

					|| pipe->stream->update_flags.raw)

				&& hws->funcs.program_all_writeback_pipes_in_tree)

			hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

	}

}

}



void dcn20_post_unlock_program_front_end(

		struct dc *dc,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

+11 −1
Original line number Diff line number Diff line
@@ -398,12 +398,22 @@ void dcn30_program_all_writeback_pipes_in_tree( 
			for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {

				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];



				if (!pipe_ctx->plane_state)

					continue;



				if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {

					wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

					break;

				}

			}

			ASSERT(wb_info.mpcc_inst != -1);



			if (wb_info.mpcc_inst == -1) {

				/* Disable writeback pipe and disconnect from MPCC

				 * if source plane has been removed

				 */

				dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);

				continue;

			}



			ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);

			dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];