Commit 8240a9b4 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/rockchip' 

- Use dev_err_probe() in dw-rockchip probe error path so the failures
  aren't silent (Uwe Kleine-König)

- Sleep PCIE_T_PVPERL_MS (100ms) before deasserting PERST# (Damien Le Moal)

- Sleep PCIE_T_RRS_READY_MS (100ms) after conventional reset, before a
  config access (Damien Le Moal)

- Request the PERST# GPIO with GPIOD_OUT_LOW so it matches the POR value,
  which avoids a spurious PERST# assertion and fixes a Qcom modem firmware
  crash and issues with WLAN controllers, e.g., RTL8822CE (Manivannan
  Sadhasivam for rockchip, Niklas Cassel for dw-rockchip)

- Refactor dw-rockchip and add support for Endpoint mode for rk3568 and
  rk3588 (Niklas Cassel)

* pci/controller/rockchip:
  PCI: dw-rockchip: Use pci_epc_init_notify() directly
  PCI: dw-rockchip: Add endpoint mode support
  PCI: dw-rockchip: Refactor the driver to prepare for EP mode
  PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
  PCI: dw-rockchip: Fix weird indentation
  PCI: dw-rockchip: Fix initial PERST# GPIO value
  PCI: dw-rockchip: Add error messages in .probe() error paths
  PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpio
  PCI: rockchip-host: Wait 100ms after reset before starting configuration
  PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
parents 59dd7046 84e30b87

drivers/pci/controller/dwc/Kconfig

+18 −4
Original line number Diff line number Diff line
@@ -311,16 +311,30 @@ config PCIE_RCAR_GEN4_EP 
	  SoCs. To compile this driver as a module, choose M here: the module

	  will be called pcie-rcar-gen4.ko. This uses the DesignWare core.



config PCIE_ROCKCHIP_DW

	bool



config PCIE_ROCKCHIP_DW_HOST

	bool "Rockchip DesignWare PCIe controller"

	select PCIE_DW

	select PCIE_DW_HOST

	bool "Rockchip DesignWare PCIe controller (host mode)"

	depends on PCI_MSI

	depends on ARCH_ROCKCHIP || COMPILE_TEST

	depends on OF

	select PCIE_DW_HOST

	select PCIE_ROCKCHIP_DW

	help

	  Enables support for the DesignWare PCIe controller in the

	  Rockchip SoC (except RK3399) to work in host mode.



config PCIE_ROCKCHIP_DW_EP

	bool "Rockchip DesignWare PCIe controller (endpoint mode)"

	depends on ARCH_ROCKCHIP || COMPILE_TEST

	depends on OF

	depends on PCI_ENDPOINT

	select PCIE_DW_EP

	select PCIE_ROCKCHIP_DW

	help

	  Enables support for the DesignWare PCIe controller in the

	  Rockchip SoC except RK3399.

	  Rockchip SoC (except RK3399) to work in endpoint mode.



config PCI_EXYNOS

	tristate "Samsung Exynos PCIe controller"

drivers/pci/controller/dwc/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o 
obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o

obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o

obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o

obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o

obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rockchip.o

obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o

obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o

obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o

drivers/pci/controller/dwc/pcie-dw-rockchip.c

+292 −38
Original line number Diff line number Diff line
@@ -34,10 +34,16 @@ 
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)



#define PCIE_CLIENT_RC_MODE		HIWORD_UPDATE_BIT(0x40)

#define PCIE_CLIENT_EP_MODE		HIWORD_UPDATE(0xf0, 0x0)

#define PCIE_CLIENT_ENABLE_LTSSM	HIWORD_UPDATE_BIT(0xc)

#define PCIE_CLIENT_DISABLE_LTSSM	HIWORD_UPDATE(0x0c, 0x8)

#define PCIE_CLIENT_INTR_STATUS_MISC	0x10

#define PCIE_CLIENT_INTR_MASK_MISC	0x24

#define PCIE_SMLH_LINKUP		BIT(16)

#define PCIE_RDLH_LINKUP		BIT(17)

#define PCIE_LINKUP			(PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)

#define PCIE_RDLH_LINK_UP_CHGED		BIT(1)

#define PCIE_LINK_REQ_RST_NOT_INT	BIT(2)

#define PCIE_L0S_ENTRY			0x11

#define PCIE_CLIENT_GENERAL_CONTROL	0x0

#define PCIE_CLIENT_INTR_STATUS_LEGACY	0x8
@@ -58,16 +64,21 @@ struct rockchip_pcie { 
	struct gpio_desc *rst_gpio;

	struct regulator *vpcie3v3;

	struct irq_domain *irq_domain;

	const struct rockchip_pcie_of_data *data;

};



static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,

					     u32 reg)

struct rockchip_pcie_of_data {

	enum dw_pcie_device_mode mode;

	const struct pci_epc_features *epc_features;

};



static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)

{

	return readl_relaxed(rockchip->apb_base + reg);

}



static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip,

						u32 val, u32 reg)

static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val,

				     u32 reg)

{

	writel_relaxed(val, rockchip->apb_base + reg);

}
@@ -144,16 +155,27 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) 
	return 0;

}



static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)

{

	return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);

}



static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)

{

	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,

				 PCIE_CLIENT_GENERAL_CONTROL);

}



static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)

{

	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,

				 PCIE_CLIENT_GENERAL_CONTROL);

}



static int rockchip_pcie_link_up(struct dw_pcie *pci)

{

	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);

	u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);

	u32 val = rockchip_pcie_get_ltssm(rockchip);



	if ((val & PCIE_LINKUP) == PCIE_LINKUP &&

	    (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
@@ -186,12 +208,18 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci) 
	return 0;

}



static void rockchip_pcie_stop_link(struct dw_pcie *pci)

{

	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);



	rockchip_pcie_disable_ltssm(rockchip);

}



static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);

	struct device *dev = rockchip->pci.dev;

	u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);

	int irq, ret;



	irq = of_irq_get_byname(dev->of_node, "legacy");
@@ -205,12 +233,6 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) 
	irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,

					 rockchip);



	/* LTSSM enable control mode */

	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);



	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,

				 PCIE_CLIENT_GENERAL_CONTROL);



	return 0;

}
@@ -218,6 +240,82 @@ static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { 
	.init = rockchip_pcie_host_init,

};



static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)

{

	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);

	enum pci_barno bar;



	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)

		dw_pcie_ep_reset_bar(pci, bar);

};



static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,

				   unsigned int type, u16 interrupt_num)

{

	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);



	switch (type) {

	case PCI_IRQ_INTX:

		return dw_pcie_ep_raise_intx_irq(ep, func_no);

	case PCI_IRQ_MSI:

		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);

	case PCI_IRQ_MSIX:

		return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);

	default:

		dev_err(pci->dev, "UNKNOWN IRQ type\n");

	}



	return 0;

}



static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {

	.linkup_notifier = true,

	.msi_capable = true,

	.msix_capable = true,

	.align = SZ_64K,

	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

};



/*

 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of

 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,

 * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by

 * default.) If the host could write to BAR4, the iATU settings (for all other

 * BARs) would be overwritten, resulting in (all other BARs) no longer working.

 */

static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {

	.linkup_notifier = true,

	.msi_capable = true,

	.msix_capable = true,

	.align = SZ_64K,

	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

	.bar[BAR_4] = { .type = BAR_RESERVED, },

	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },

};



static const struct pci_epc_features *

rockchip_pcie_get_features(struct dw_pcie_ep *ep)

{

	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);

	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);



	return rockchip->data->epc_features;

}



static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {

	.init = rockchip_pcie_ep_init,

	.raise_irq = rockchip_pcie_raise_irq,

	.get_features = rockchip_pcie_get_features,

};



static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)

{

	struct device *dev = rockchip->pci.dev;
@@ -225,11 +323,15 @@ static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip) 


	ret = devm_clk_bulk_get_all(dev, &rockchip->clks);

	if (ret < 0)

		return ret;

		return dev_err_probe(dev, ret, "failed to get clocks\n");



	rockchip->clk_cnt = ret;



	return clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);

	ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);

	if (ret)

		return dev_err_probe(dev, ret, "failed to enable clocks\n");



	return 0;

}



static int rockchip_pcie_resource_get(struct platform_device *pdev,
@@ -237,12 +339,14 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev, 
{

	rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");

	if (IS_ERR(rockchip->apb_base))

		return PTR_ERR(rockchip->apb_base);

		return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base),

				     "failed to map apb registers\n");



	rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",

						     GPIOD_OUT_HIGH);

						     GPIOD_OUT_LOW);

	if (IS_ERR(rockchip->rst_gpio))

		return PTR_ERR(rockchip->rst_gpio);

		return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst_gpio),

				     "failed to get reset gpio\n");



	rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);

	if (IS_ERR(rockchip->rst))
@@ -282,15 +386,127 @@ static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) 
static const struct dw_pcie_ops dw_pcie_ops = {

	.link_up = rockchip_pcie_link_up,

	.start_link = rockchip_pcie_start_link,

	.stop_link = rockchip_pcie_stop_link,

};



static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)

{

	struct rockchip_pcie *rockchip = arg;

	struct dw_pcie *pci = &rockchip->pci;

	struct device *dev = pci->dev;

	u32 reg, val;



	reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);

	rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);



	dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);

	dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));



	if (reg & PCIE_LINK_REQ_RST_NOT_INT) {

		dev_dbg(dev, "hot reset or link-down reset\n");

		dw_pcie_ep_linkdown(&pci->ep);

	}



	if (reg & PCIE_RDLH_LINK_UP_CHGED) {

		val = rockchip_pcie_get_ltssm(rockchip);

		if ((val & PCIE_LINKUP) == PCIE_LINKUP) {

			dev_dbg(dev, "link up\n");

			dw_pcie_ep_linkup(&pci->ep);

		}

	}



	return IRQ_HANDLED;

}



static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip)

{

	struct dw_pcie_rp *pp;

	u32 val;



	if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))

		return -ENODEV;



	/* LTSSM enable control mode */

	val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);

	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);



	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,

				 PCIE_CLIENT_GENERAL_CONTROL);



	pp = &rockchip->pci.pp;

	pp->ops = &rockchip_pcie_host_ops;



	return dw_pcie_host_init(pp);

}



static int rockchip_pcie_configure_ep(struct platform_device *pdev,

				      struct rockchip_pcie *rockchip)

{

	struct device *dev = &pdev->dev;

	int irq, ret;

	u32 val;



	if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))

		return -ENODEV;



	irq = platform_get_irq_byname(pdev, "sys");

	if (irq < 0) {

		dev_err(dev, "missing sys IRQ resource\n");

		return irq;

	}



	ret = devm_request_threaded_irq(dev, irq, NULL,

					rockchip_pcie_ep_sys_irq_thread,

					IRQF_ONESHOT, "pcie-sys", rockchip);

	if (ret) {

		dev_err(dev, "failed to request PCIe sys IRQ\n");

		return ret;

	}



	/* LTSSM enable control mode */

	val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);

	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);



	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,

				 PCIE_CLIENT_GENERAL_CONTROL);



	rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;

	rockchip->pci.ep.page_size = SZ_64K;



	dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));



	ret = dw_pcie_ep_init(&rockchip->pci.ep);

	if (ret) {

		dev_err(dev, "failed to initialize endpoint\n");

		return ret;

	}



	ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);

	if (ret) {

		dev_err(dev, "failed to initialize DWC endpoint registers\n");

		dw_pcie_ep_deinit(&rockchip->pci.ep);

		return ret;

	}



	pci_epc_init_notify(rockchip->pci.ep.epc);



	/* unmask DLL up/down indicator and hot reset/link-down reset */

	rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC);



	return ret;

}



static int rockchip_pcie_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct rockchip_pcie *rockchip;

	struct dw_pcie_rp *pp;

	const struct rockchip_pcie_of_data *data;

	int ret;



	data = of_device_get_match_data(dev);

	if (!data)

		return -EINVAL;



	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);

	if (!rockchip)

		return -ENOMEM;
@@ -299,9 +515,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) 


	rockchip->pci.dev = dev;

	rockchip->pci.ops = &dw_pcie_ops;



	pp = &rockchip->pci.pp;

	pp->ops = &rockchip_pcie_host_ops;

	rockchip->data = data;



	ret = rockchip_pcie_resource_get(pdev, rockchip);

	if (ret)
@@ -320,10 +534,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev) 
		rockchip->vpcie3v3 = NULL;

	} else {

		ret = regulator_enable(rockchip->vpcie3v3);

		if (ret) {

			dev_err(dev, "failed to enable vpcie3v3 regulator\n");

			return ret;

		}

		if (ret)

			return dev_err_probe(dev, ret,

					     "failed to enable vpcie3v3 regulator\n");

	}



	ret = rockchip_pcie_phy_init(rockchip);
@@ -338,10 +551,26 @@ static int rockchip_pcie_probe(struct platform_device *pdev) 
	if (ret)

		goto deinit_phy;



	ret = dw_pcie_host_init(pp);

	if (!ret)

	switch (data->mode) {

	case DW_PCIE_RC_TYPE:

		ret = rockchip_pcie_configure_rc(rockchip);

		if (ret)

			goto deinit_clk;

		break;

	case DW_PCIE_EP_TYPE:

		ret = rockchip_pcie_configure_ep(pdev, rockchip);

		if (ret)

			goto deinit_clk;

		break;

	default:

		dev_err(dev, "INVALID device type %d\n", data->mode);

		ret = -EINVAL;

		goto deinit_clk;

	}



	return 0;



deinit_clk:

	clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);

deinit_phy:

	rockchip_pcie_phy_deinit(rockchip);
@@ -352,8 +581,33 @@ static int rockchip_pcie_probe(struct platform_device *pdev) 
	return ret;

}



static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {

	.mode = DW_PCIE_RC_TYPE,

};



static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = {

	.mode = DW_PCIE_EP_TYPE,

	.epc_features = &rockchip_pcie_epc_features_rk3568,

};



static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = {

	.mode = DW_PCIE_EP_TYPE,

	.epc_features = &rockchip_pcie_epc_features_rk3588,

};



static const struct of_device_id rockchip_pcie_of_match[] = {

	{ .compatible = "rockchip,rk3568-pcie", },

	{

		.compatible = "rockchip,rk3568-pcie",

		.data = &rockchip_pcie_rc_of_data_rk3568,

	},

	{

		.compatible = "rockchip,rk3568-pcie-ep",

		.data = &rockchip_pcie_ep_of_data_rk3568,

	},

	{

		.compatible = "rockchip,rk3588-pcie-ep",

		.data = &rockchip_pcie_ep_of_data_rk3588,

	},

	{},

};

drivers/pci/controller/pcie-rockchip-host.c

+3 −0
Original line number Diff line number Diff line
@@ -322,8 +322,11 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) 
	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,

			    PCIE_CLIENT_CONFIG);



	msleep(PCIE_T_PVPERL_MS);

	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);



	msleep(PCIE_T_RRS_READY_MS);



	/* 500ms timeout value should be enough for Gen1/2 training */

	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,

				 status, PCIE_LINK_UP(status), 20,

drivers/pci/controller/pcie-rockchip.c

+1 −1
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 


	if (rockchip->is_rc) {

		rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",

							    GPIOD_OUT_HIGH);

							    GPIOD_OUT_LOW);

		if (IS_ERR(rockchip->ep_gpio))

			return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),

					     "failed to get ep GPIO\n");