Commit 8248ca30 authored by Ley Foon Tan's avatar Ley Foon Tan Committed by Daniel Lezcano
Browse files

clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization 



In the RISC-V specification, the stimecmp register doesn't have a default
value. To prevent the timer interrupt from being triggered during timer
initialization, clear the timer interrupt by writing stimecmp with a
maximum value.

Fixes: 9f7a8ff6 ("RISC-V: Prefer sstc extension if available")
Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarLey Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Tested-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@starfivetech.com
parent c819dbd0

drivers/clocksource/timer-riscv.c

+3 −0
Original line number Diff line number Diff line
@@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu) 
{

	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);



	/* Clear timer interrupt */

	riscv_clock_event_stop();



	ce->cpumask = cpumask_of(cpu);

	ce->irq = riscv_clock_event_irq;

	if (riscv_timer_cannot_wake_cpu)