Commit 8265ce0e authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM 



We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3 retries"
since we started configuring LFPS sending. According to Bspec Configuring
LFPS sending is needed only when using AUXLess ALPM. This patch avoids
these failures by configuring LFPS sending only when using AUXLess ALPM.

Bspec: 68849
Fixes: 9dc61968 ("drm/i915/display: Add function to configure LFPS sending")
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-2-jouni.hogander@intel.com
parent 17133255

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+3 −5
Original line number Diff line number Diff line
@@ -3240,11 +3240,10 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, 
{

	struct intel_display *display = to_intel_display(encoder);

	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);

	bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),

						  crtc_state);

	int i;



	if (DISPLAY_VER(display) < 20)

	if (DISPLAY_VER(display) < 20 ||

	    !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))

		return;



	for (i = 0; i < 4; i++) {
@@ -3256,8 +3255,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, 


		intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),

			      CONTROL0_MAC_TRANSMIT_LFPS,

			      enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,

			      MB_WRITE_COMMITTED);

			      CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);

	}

}