Commit 829f21e9 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx12.1: add support for disable_kq 



Plumb in support for disabling kernel queues and make it
the default.  For testing, kernel queues can be re-enabled
by setting amdgpu.user_queue=0

v2: integrate feedback from Lijo

Acked-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f5a05f84

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

+71 −19
Original line number Diff line number Diff line
@@ -1155,11 +1155,13 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 
		break;

	}



	if (adev->gfx.num_compute_rings) {

		/* recalculate compute rings to use based on hardware configuration */

		num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *

				     adev->gfx.mec.num_queue_per_pipe) / 2;

		adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,

						  num_compute_rings);

	}



	num_xcc = NUM_XCC(adev->gfx.xcc_mask);
@@ -2794,6 +2796,33 @@ static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, 
	gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);

}



static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev,

					      bool enable)

{

	unsigned int irq_type;

	int m, p, r;



	if (adev->gfx.disable_kq) {

		for (m = 0; m < adev->gfx.mec.num_mec; ++m) {

			for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {

				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP

					+ (m * adev->gfx.mec.num_pipe_per_mec)

					+ p;

				if (enable)

					r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,

							   irq_type);

				else

					r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,

							   irq_type);

				if (r)

					return r;

			}

		}

	}



	return 0;

}



static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = ip_block->adev;
@@ -2801,6 +2830,7 @@ static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 


	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);

	gfx_v12_1_set_userq_eop_interrupts(adev, false);



	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {
@@ -2868,8 +2898,24 @@ static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) 
{

	struct amdgpu_device *adev = ip_block->adev;





	switch (amdgpu_user_queue) {

	case -1:

	default:

		adev->gfx.disable_kq = true;

		adev->gfx.disable_uq = true;

		break;

	case 0:

		adev->gfx.disable_kq = false;

		adev->gfx.disable_uq = true;

		break;

	}



	adev->gfx.funcs = &gfx_v12_1_gfx_funcs;



	if (adev->gfx.disable_kq)

		adev->gfx.num_compute_rings = 0;

	else

		adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),

						  AMDGPU_MAX_COMPUTE_RINGS);
@@ -2898,6 +2944,10 @@ static int gfx_v12_1_late_init(struct amdgpu_ip_block *ip_block) 
	if (r)

		return r;



	r = gfx_v12_1_set_userq_eop_interrupts(adev, true);

	if (r)

		return r;



	return 0;

}
@@ -3716,6 +3766,7 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, 
	if (xcc_id == -EINVAL)

		return;



	if (!adev->gfx.disable_kq) {

		switch (me_id) {

		case 1:

		case 2:
@@ -3733,6 +3784,7 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, 
			break;

		}

	}

}



static int gfx_v12_1_priv_reg_irq(struct amdgpu_device *adev,

				  struct amdgpu_irq_src *source,