Commit 82a32eac authored by Zenghui Yu (Huawei)'s avatar Zenghui Yu (Huawei) Committed by Marc Zyngier
Browse files

KVM: arm64: Fix various comments 



Use tab instead of whitespaces, as well as 2 minor typo fixes.

Signed-off-by: default avatarZenghui Yu (Huawei) <zenghui.yu@linux.dev>
Link: https://patch.msgid.link/20260128075208.23024-1-zenghui.yu@linux.dev


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 9d46e83a

arch/arm64/kvm/hyp/vhe/sysreg-sr.c

+1 −1
Original line number Diff line number Diff line
@@ -205,7 +205,7 @@ void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu) 


	/*

	 * When running a normal EL1 guest, we only load a new vcpu

	 * after a context switch, which imvolves a DSB, so all

	 * after a context switch, which involves a DSB, so all

	 * speculative EL1&0 walks will have already completed.

	 * If running NV, the vcpu may transition between vEL1 and

	 * vEL2 without a context switch, so make sure we complete

arch/arm64/kvm/vgic/vgic-v3-nested.c

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ static int lr_map_idx_to_shadow_idx(struct shadow_if *shadow_if, int idx) 
 * as the L1 guest is in charge of provisioning the interrupts via its own

 * view of the ICH_LR*_EL2 registers, which conveniently live in the VNCR

 * page.  This means that the flow described above does work (there is no

 * state to rebuild in the L0 hypervisor), and that most things happed on L2

 * state to rebuild in the L0 hypervisor), and that most things happen on L2

 * load/put:

 *

 * - on L2 load: move the in-memory L1 vGIC configuration into a shadow,

arch/arm64/include/asm/kvm_host.h

+1 −1

File changed.

Contains only whitespace changes.