Commit 82caa1c8 authored by Uma Shankar's avatar Uma Shankar Committed by Jani Nikula
Browse files

drm/i915/color: Program Pre-CSC registers 



Add callback to program Pre-CSC LUT for TGL and beyond

v2: Add DSB support
v3: Add support for single segment 1D LUT color op
v4:
- s/drm_color_lut_32/drm_color_lut32/ (Simon)
- Change commit message (Suraj)
- Improve comments (Suraj)
- Remove multisegmented programming, to be added later
- Remove dead code for SDR planes, add when needed

BSpec: 50411, 50412, 50413, 50414
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20251203085211.3663374-12-uma.shankar@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 3b7476e7

drivers/gpu/drm/i915/display/intel_color.c

+61 −0
Original line number Diff line number Diff line
@@ -3943,6 +3943,66 @@ xelpd_load_plane_csc_matrix(struct intel_dsb *dsb, 
			   ctm_to_twos_complement(input[11], 0, 12));

}



static void

xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,

				const struct intel_plane_state *plane_state)

{

	struct intel_display *display = to_intel_display(plane_state);

	const struct drm_plane_state *state = &plane_state->uapi;

	enum pipe pipe = to_intel_plane(state->plane)->pipe;

	enum plane_id plane = to_intel_plane(state->plane)->id;

	const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;

	u32 i, lut_size;



	if (icl_is_hdr_plane(display, plane)) {

		lut_size = 128;



		intel_de_write_dsb(display, dsb,

				   PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0),

				   PLANE_PAL_PREC_AUTO_INCREMENT);



		if (pre_csc_lut) {

			for (i = 0; i < lut_size; i++) {

				u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);



				intel_de_write_dsb(display, dsb,

						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),

						   lut_val);

			}



			/* Program the max register to clamp values > 1.0. */

			/* TODO: Restrict to 0x7ffffff */

			do {

				intel_de_write_dsb(display, dsb,

						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),

						   (1 << 24));

			} while (i++ > 130);

		} else {

			for (i = 0; i < lut_size; i++) {

				u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);



				intel_de_write_dsb(display, dsb,

						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);

			}



			do {

				intel_de_write_dsb(display, dsb,

						   PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),

						   1 << 24);

			} while (i++ < 130);

		}



		intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);

	}

}



static void

xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)

{

	if (plane_state->hw.degamma_lut)

		xelpd_program_plane_pre_csc_lut(dsb, plane_state);

}



static const struct intel_color_funcs chv_color_funcs = {

	.color_check = chv_color_check,

	.color_commit_arm = i9xx_color_commit_arm,
@@ -3991,6 +4051,7 @@ static const struct intel_color_funcs tgl_color_funcs = { 
	.read_csc = icl_read_csc,

	.get_config = skl_get_config,

	.load_plane_csc_matrix = xelpd_load_plane_csc_matrix,

	.load_plane_luts = xelpd_plane_load_luts,

};



static const struct intel_color_funcs icl_color_funcs = {