Commit 8322aded authored by Ashutosh Dixit's avatar Ashutosh Dixit
Browse files

drm/xe/rtp: Whitelist OAM MMIO trigger registers 



Whitelist OAM registers to enable userspace to execute MMIO triggers on OAM
units.

Signed-off-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patch.msgid.link/20251202025115.373546-6-ashutosh.dixit@intel.com
parent ed455775

drivers/gpu/drm/xe/regs/xe_oa_regs.h

+8 −0
Original line number Diff line number Diff line
@@ -100,4 +100,12 @@ 
#define OAM_COMPRESSION_T3_CONTROL		XE_REG(0x1c2e00)

#define  OAM_LAT_MEASURE_ENABLE			REG_BIT(4)



/* Actual address is MEDIA_GT_GSI_OFFSET + the base addr below */

#define XE_OAM_SAG_BASE				0x13000

#define XE_OAM_SCMI_0_BASE			0x14000

#define XE_OAM_SCMI_1_BASE			0x14800

#define XE_OAM_SAG_BASE_ADJ			(MEDIA_GT_GSI_OFFSET + XE_OAM_SAG_BASE)

#define XE_OAM_SCMI_0_BASE_ADJ			(MEDIA_GT_GSI_OFFSET + XE_OAM_SCMI_0_BASE)

#define XE_OAM_SCMI_1_BASE_ADJ			(MEDIA_GT_GSI_OFFSET + XE_OAM_SCMI_1_BASE)



#endif

drivers/gpu/drm/xe/xe_oa.c

+3 −4
Original line number Diff line number Diff line
@@ -2601,11 +2601,10 @@ static struct xe_oa_regs __oag_regs(void) 


static void __xe_oa_init_oa_units(struct xe_gt *gt)

{

	/* Actual address is MEDIA_GT_GSI_OFFSET + oam_base_addr[i] */

	const u32 oam_base_addr[] = {

		[XE_OAM_UNIT_SAG]    = 0x13000,

		[XE_OAM_UNIT_SCMI_0] = 0x14000,

		[XE_OAM_UNIT_SCMI_1] = 0x14800,

		[XE_OAM_UNIT_SAG]    = XE_OAM_SAG_BASE,

		[XE_OAM_UNIT_SCMI_0] = XE_OAM_SCMI_0_BASE,

		[XE_OAM_UNIT_SCMI_1] = XE_OAM_SCMI_1_BASE,

	};

	int i, num_units = gt->oa.num_oa_units;

drivers/gpu/drm/xe/xe_reg_whitelist.c

+21 −0
Original line number Diff line number Diff line
@@ -83,6 +83,17 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { 
#define WHITELIST_OAG_MMIO_TRG \

	WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)



#define WHITELIST_OAM_MMIO_TRG \

	WHITELIST_OA_MMIO_TRG(OAM_MMIO_TRG(XE_OAM_SAG_BASE_ADJ), \

			      OAM_STATUS(XE_OAM_SAG_BASE_ADJ), \

			      OAM_HEAD_POINTER(XE_OAM_SAG_BASE_ADJ)), \

	WHITELIST_OA_MMIO_TRG(OAM_MMIO_TRG(XE_OAM_SCMI_0_BASE_ADJ), \

			      OAM_STATUS(XE_OAM_SCMI_0_BASE_ADJ), \

			      OAM_HEAD_POINTER(XE_OAM_SCMI_0_BASE_ADJ)), \

	WHITELIST_OA_MMIO_TRG(OAM_MMIO_TRG(XE_OAM_SCMI_1_BASE_ADJ), \

			      OAM_STATUS(XE_OAM_SCMI_1_BASE_ADJ), \

			      OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ))



	{ XE_RTP_NAME("oag_mmio_trg_rcs"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),

		       ENGINE_CLASS(RENDER)),
@@ -93,6 +104,16 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { 
		       ENGINE_CLASS(COMPUTE)),

	  XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG)

	},

	{ XE_RTP_NAME("oam_mmio_trg_vcs"),

	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, XE_RTP_END_VERSION_UNDEFINED),

		       ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(WHITELIST_OAM_MMIO_TRG)

	},

	{ XE_RTP_NAME("oam_mmio_trg_vecs"),

	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, XE_RTP_END_VERSION_UNDEFINED),

		       ENGINE_CLASS(VIDEO_ENHANCE)),

	  XE_RTP_ACTIONS(WHITELIST_OAM_MMIO_TRG)

	},

};



static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)