Commit 8368e971 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.14-2024-12-18' of... 

Merge tag 'amd-drm-next-6.14-2024-12-18' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-6.14-2024-12-18:

amdgpu:
- RAS updates
- ISP updates
- SDMA queue reset support
- Rework DPM powergating interfaces
- Documentation updates and cleanups
- Panel replay fixes
- DCN 3.5 updates
- DP tunneling fixes
- Use a pm notifier to more gracefully handle VRAM eviction on suspend or hibernate
- Add debugfs interfaces for forcing scheduling to specific engine instances
- GG 9.5 updates
- IH 4.4 updates
- Make missing optional firmware less noisy
- PSP 13.x updates
- SMU 13.x updates
- VCN 5.x updates
- JPEG 5.x updates
- Misc cleanups
- GC 12.x updates
- DRM panic support
- DC FAMS updates
- DSC fixes
- job handling fixes

amdkfd:
- GG 9.5 updates
- Logging improvements
- Misc cleanups
- Various Optimizations

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241218201758.2580723-1-alexander.deucher@amd.com
parents 38e96109 695c2c74

drivers/gpu/drm/amd/amdgpu/Makefile

+5 −3
Original line number Diff line number Diff line 
#

# Copyright 2017 Advanced Micro Devices, Inc.

# Copyright 2017-2024 Advanced Micro Devices, Inc. All rights reserved.

#

# Permission is hereby granted, free of charge, to any person obtaining a

# copy of this software and associated documentation files (the "Software"),
@@ -105,7 +105,7 @@ amdgpu-y += \ 


# add UMC block

amdgpu-y += \

	umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o umc_v12_0.o

	umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o umc_v12_0.o umc_v8_14.o



# add IH block

amdgpu-y += \
@@ -200,6 +200,7 @@ amdgpu-y += \ 
	vcn_v4_0_3.o \

	vcn_v4_0_5.o \

	vcn_v5_0_0.o \

	vcn_v5_0_1.o \

	amdgpu_jpeg.o \

	jpeg_v1_0.o \

	jpeg_v2_0.o \
@@ -208,7 +209,8 @@ amdgpu-y += \ 
	jpeg_v4_0.o \

	jpeg_v4_0_3.o \

	jpeg_v4_0_5.o \

	jpeg_v5_0_0.o

	jpeg_v5_0_0.o \

	jpeg_v5_0_1.o



# add VPE block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/aldebaran.c

+2 −0
Original line number Diff line number Diff line
@@ -334,6 +334,8 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 
				AMDGPU_INIT_LEVEL_RESET_RECOVERY);

		dev_info(tmp_adev->dev,

			 "GPU reset succeeded, trying to resume\n");

		/*TBD: Ideally should clear only GFX, SDMA blocks*/

		amdgpu_ras_clear_err_state(tmp_adev);

		r = aldebaran_mode2_restore_ip(tmp_adev);

		if (r)

			goto end;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -880,6 +880,7 @@ struct amdgpu_device { 
	bool				need_swiotlb;

	bool				accel_working;

	struct notifier_block		acpi_nb;

	struct notifier_block		pm_nb;

	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];

	struct debugfs_blob_wrapper     debugfs_vbios_blob;

	struct debugfs_blob_wrapper     debugfs_discovery_blob;
@@ -1174,7 +1175,6 @@ struct amdgpu_device { 


	struct work_struct		reset_work;



	bool                            job_hang;

	bool                            dc_enabled;

	/* Mask of active clusters */

	uint32_t			aid_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

+5 −0
Original line number Diff line number Diff line
@@ -71,6 +71,11 @@ struct ras_query_context; 
#define ACA_ERROR_CE_MASK		BIT_MASK(ACA_ERROR_TYPE_CE)

#define ACA_ERROR_DEFERRED_MASK		BIT_MASK(ACA_ERROR_TYPE_DEFERRED)



#define mmSMNAID_AID0_MCA_SMU		0x03b30400	/* SMN AID AID0 */

#define mmSMNAID_XCD0_MCA_SMU		0x36430400	/* SMN AID XCD0 */

#define mmSMNAID_XCD1_MCA_SMU		0x38430400	/* SMN AID XCD1 */

#define mmSMNXCD_XCD0_MCA_SMU		0x40430400	/* SMN XCD XCD0 */



enum aca_reg_idx {

	ACA_REG_IDX_CTL			= 0,

	ACA_REG_IDX_STATUS		= 1,

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+10 −10
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ static int acp_poweroff(struct generic_pm_domain *genpd) 
	 * 2. power off the acp tiles

	 * 3. check and enter ulv state

	 */

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

	return 0;

}
@@ -157,7 +157,7 @@ static int acp_poweron(struct generic_pm_domain *genpd) 
	 * 2. turn on acp clock

	 * 3. power on acp tiles

	 */

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);

	return 0;

}
@@ -236,7 +236,7 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) 
			    ip_block->version->major, ip_block->version->minor);

	/* -ENODEV means board uses AZ rather than ACP */

	if (r == -ENODEV) {

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

		return 0;

	} else if (r) {

		return r;
@@ -508,7 +508,7 @@ static int acp_hw_fini(struct amdgpu_ip_block *ip_block) 


	/* return early if no ACP */

	if (!adev->acp.acp_genpd) {

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);

		return 0;

	}
@@ -565,7 +565,7 @@ static int acp_suspend(struct amdgpu_ip_block *ip_block) 


	/* power up on suspend */

	if (!adev->acp.acp_cell)

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);

	return 0;

}
@@ -575,7 +575,7 @@ static int acp_resume(struct amdgpu_ip_block *ip_block) 


	/* power down again on resume */

	if (!adev->acp.acp_cell)

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);

		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

	return 0;

}
@@ -584,19 +584,19 @@ static bool acp_is_idle(void *handle) 
	return true;

}



static int acp_set_clockgating_state(void *handle,

static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block,

				     enum amd_clockgating_state state)

{

	return 0;

}



static int acp_set_powergating_state(void *handle,

static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,

				     enum amd_powergating_state state)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_device *adev = ip_block->adev;

	bool enable = (state == AMD_PG_STATE_GATE);



	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);



	return 0;

}