Commit 83a0c342 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid 



The number of queue per pipe for mec on sienna_cichlid should be 4.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a346ef86

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+8 −1
Original line number Diff line number Diff line
@@ -4147,7 +4147,6 @@ static int gfx_v10_0_sw_init(void *handle) 
	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_SIENNA_CICHLID:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;
@@ -4155,6 +4154,14 @@ static int gfx_v10_0_sw_init(void *handle) 
		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 8;

		break;

	case CHIP_SIENNA_CICHLID:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 2;

		adev->gfx.me.num_queue_per_pipe = 1;

		adev->gfx.mec.num_mec = 2;

		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

		break;

	default:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;