Commit 8409495b authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: cores: remove many xxx_SHIFT definitions 



We have many xxx_SHIFT definitions along side their corresponding
xxx_MASK definitions for the various cores. Manually using the
shift and mask can be error prone, as shown with the dwmac4 RXFSTS
fix patch.

Convert sites that use xxx_SHIFT and xxx_MASK directly to use
FIELD_GET(), FIELD_PREP(), and u32_replace_bits() as appropriate.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vdtw8-00000002Gtu-0Hyu@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 670d1050

drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c

+2 −3
Original line number Diff line number Diff line
@@ -192,9 +192,8 @@ static void loongson_dwmac_dma_init_channel(struct stmmac_priv *priv, 
		value |= DMA_BUS_MODE_MAXPBL;



	value |= DMA_BUS_MODE_USP;

	value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);

	value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);

	value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);

	value = u32_replace_bits(value, txpbl, DMA_BUS_MODE_PBL_MASK);

	value = u32_replace_bits(value, rxpbl, DMA_BUS_MODE_RPBL_MASK);



	/* Set the Fixed burst mode */

	if (dma_cfg->fixed_burst)

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

+2 −3
Original line number Diff line number Diff line
@@ -367,9 +367,8 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system, 
		.use_nsecs = false,

	};



	num_snapshot = (readl(ioaddr + XGMAC_TIMESTAMP_STATUS) &

			XGMAC_TIMESTAMP_ATSNS_MASK) >>

			XGMAC_TIMESTAMP_ATSNS_SHIFT;

	num_snapshot = FIELD_GET(XGMAC_TIMESTAMP_ATSNS_MASK,

				 readl(ioaddr + XGMAC_TIMESTAMP_STATUS));



	/* Repeat until the timestamps are from the FIFO last segment */

	for (i = 0; i < num_snapshot; i++) {

drivers/net/ethernet/stmicro/stmmac/dwmac100.h

+3 −6
Original line number Diff line number Diff line
@@ -59,8 +59,7 @@ 
#define MAC_CORE_INIT (MAC_CONTROL_HBD)



/* MAC FLOW CTRL defines */

#define MAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */

#define MAC_FLOW_CTRL_PT_SHIFT	16

#define MAC_FLOW_CTRL_PT_MASK	GENMASK(31, 16)	/* Pause Time Mask */

#define MAC_FLOW_CTRL_PASS	0x00000004	/* Pass Control Frames */

#define MAC_FLOW_CTRL_ENABLE	0x00000002	/* Flow Control Enable */

#define MAC_FLOW_CTRL_PAUSE	0x00000001	/* Flow Control Busy ... */
@@ -76,10 +75,8 @@ 
/* DMA Bus Mode register defines */

#define DMA_BUS_MODE_DBO	0x00100000	/* Descriptor Byte Ordering */

#define DMA_BUS_MODE_BLE	0x00000080	/* Big Endian/Little Endian */

#define DMA_BUS_MODE_PBL_MASK	0x00003f00	/* Programmable Burst Len */

#define DMA_BUS_MODE_PBL_SHIFT	8

#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */

#define DMA_BUS_MODE_DSL_SHIFT	2	/*   (in DWORDS)      */

#define DMA_BUS_MODE_PBL_MASK	GENMASK(13, 8)	/* Programmable Burst Len */

#define DMA_BUS_MODE_DSL_MASK	GENMASK(6, 2)	/* Descriptor Skip Length */

#define DMA_BUS_MODE_BAR_BUS	0x00000002	/* Bar-Bus Arbitration */

#define DMA_BUS_MODE_DEFAULT	0x00000000

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+3 −13
Original line number Diff line number Diff line
@@ -76,7 +76,6 @@ enum power_event { 
/* SGMII/RGMII status register */

#define GMAC_RGSMIIIS_LNKMODE		BIT(0)

#define GMAC_RGSMIIIS_SPEED		GENMASK(2, 1)

#define GMAC_RGSMIIIS_SPEED_SHIFT	1

#define GMAC_RGSMIIIS_LNKSTS		BIT(3)

#define GMAC_RGSMIIIS_JABTO		BIT(4)

#define GMAC_RGSMIIIS_FALSECARDET	BIT(5)
@@ -133,8 +132,7 @@ enum inter_frame_gap { 
#define GMAC_MII_ADDR_WRITE	0x00000002	/* MII Write */

#define GMAC_MII_ADDR_BUSY	0x00000001	/* MII Busy */

/* GMAC FLOW CTRL defines */

#define GMAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */

#define GMAC_FLOW_CTRL_PT_SHIFT	16

#define GMAC_FLOW_CTRL_PT_MASK	GENMASK(31, 16)	/* Pause Time Mask */

#define GMAC_FLOW_CTRL_UP	0x00000008	/* Unicast pause frame enable */

#define GMAC_FLOW_CTRL_RFE	0x00000004	/* Rx Flow Control Enable */

#define GMAC_FLOW_CTRL_TFE	0x00000002	/* Tx Flow Control Enable */
@@ -147,7 +145,6 @@ enum inter_frame_gap { 
#define GMAC_DEBUG_TWCSTS	BIT(22) /* MTL Tx FIFO Write Controller */

/* MTL Tx FIFO Read Controller Status */

#define GMAC_DEBUG_TRCSTS_MASK	GENMASK(21, 20)

#define GMAC_DEBUG_TRCSTS_SHIFT	20

#define GMAC_DEBUG_TRCSTS_IDLE	0

#define GMAC_DEBUG_TRCSTS_READ	1

#define GMAC_DEBUG_TRCSTS_TXW	2
@@ -155,7 +152,6 @@ enum inter_frame_gap { 
#define GMAC_DEBUG_TXPAUSED	BIT(19) /* MAC Transmitter in PAUSE */

/* MAC Transmit Frame Controller Status */

#define GMAC_DEBUG_TFCSTS_MASK	GENMASK(18, 17)

#define GMAC_DEBUG_TFCSTS_SHIFT	17

#define GMAC_DEBUG_TFCSTS_IDLE	0

#define GMAC_DEBUG_TFCSTS_WAIT	1

#define GMAC_DEBUG_TFCSTS_GEN_PAUSE	2
@@ -163,13 +159,11 @@ enum inter_frame_gap { 
/* MAC GMII or MII Transmit Protocol Engine Status */

#define GMAC_DEBUG_TPESTS	BIT(16)

#define GMAC_DEBUG_RXFSTS_MASK	GENMASK(9, 8) /* MTL Rx FIFO Fill-level */

#define GMAC_DEBUG_RXFSTS_SHIFT	8

#define GMAC_DEBUG_RXFSTS_EMPTY	0

#define GMAC_DEBUG_RXFSTS_BT	1

#define GMAC_DEBUG_RXFSTS_AT	2

#define GMAC_DEBUG_RXFSTS_FULL	3

#define GMAC_DEBUG_RRCSTS_MASK	GENMASK(6, 5) /* MTL Rx FIFO Read Controller */

#define GMAC_DEBUG_RRCSTS_SHIFT	5

#define GMAC_DEBUG_RRCSTS_IDLE	0

#define GMAC_DEBUG_RRCSTS_RDATA	1

#define GMAC_DEBUG_RRCSTS_RSTAT	2
@@ -177,7 +171,6 @@ enum inter_frame_gap { 
#define GMAC_DEBUG_RWCSTS	BIT(4) /* MTL Rx FIFO Write Controller Active */

/* MAC Receive Frame Controller FIFO Status */

#define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)

#define GMAC_DEBUG_RFCFCSTS_SHIFT	1

/* MAC GMII or MII Receive Protocol Engine Status */

#define GMAC_DEBUG_RPESTS	BIT(0)
@@ -187,8 +180,7 @@ enum inter_frame_gap { 
#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */

#define DMA_BUS_MODE_DSL_SHIFT	2		/*   (in DWORDS)      */

/* Programmable burst length (passed thorugh platform)*/

#define DMA_BUS_MODE_PBL_MASK	0x00003f00	/* Programmable Burst Len */

#define DMA_BUS_MODE_PBL_SHIFT	8

#define DMA_BUS_MODE_PBL_MASK	GENMASK(13, 8)	/* Programmable Burst Len */

#define DMA_BUS_MODE_ATDS	0x00000080	/* Alternate Descriptor Size */



enum rx_tx_priority_ratio {
@@ -199,8 +191,7 @@ enum rx_tx_priority_ratio { 


#define DMA_BUS_MODE_FB		0x00010000	/* Fixed burst */

#define DMA_BUS_MODE_MB		0x04000000	/* Mixed burst */

#define DMA_BUS_MODE_RPBL_MASK	0x007e0000	/* Rx-Programmable Burst Len */

#define DMA_BUS_MODE_RPBL_SHIFT	17

#define DMA_BUS_MODE_RPBL_MASK	GENMASK(22, 17)	/* Rx-Programmable Burst Len */

#define DMA_BUS_MODE_USP	0x00800000

#define DMA_BUS_MODE_MAXPBL	0x01000000

#define DMA_BUS_MODE_AAL	0x02000000
@@ -320,7 +311,6 @@ enum rtc_control { 
/* PTP and timestamping registers */



#define GMAC3_X_ATSNS       GENMASK(29, 25)

#define GMAC3_X_ATSNS_SHIFT 25



#define GMAC_PTP_TCR_ATSFC	BIT(24)

#define GMAC_PTP_TCR_ATSEN0	BIT(25)

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+9 −12
Original line number Diff line number Diff line
@@ -242,7 +242,7 @@ static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, 


	if (duplex) {

		pr_debug("\tduplex mode: PAUSE %d\n", pause_time);

		flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);

		flow |= FIELD_PREP(GMAC_FLOW_CTRL_PT_MASK, pause_time);

	}



	writel(flow, ioaddr + GMAC_FLOW_CTRL);
@@ -378,8 +378,8 @@ static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr, 
	if (value & GMAC_DEBUG_TWCSTS)

		x->mmtl_fifo_ctrl++;

	if (value & GMAC_DEBUG_TRCSTS_MASK) {

		u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)

			     >> GMAC_DEBUG_TRCSTS_SHIFT;

		u32 trcsts = FIELD_GET(GMAC_DEBUG_TRCSTS_MASK, value);



		if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)

			x->mtl_tx_fifo_read_ctrl_write++;

		else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
@@ -392,8 +392,7 @@ static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr, 
	if (value & GMAC_DEBUG_TXPAUSED)

		x->mac_tx_in_pause++;

	if (value & GMAC_DEBUG_TFCSTS_MASK) {

		u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)

			      >> GMAC_DEBUG_TFCSTS_SHIFT;

		u32 tfcsts = FIELD_GET(GMAC_DEBUG_TFCSTS_MASK, value);



		if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)

			x->mac_tx_frame_ctrl_xfer++;
@@ -407,8 +406,7 @@ static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr, 
	if (value & GMAC_DEBUG_TPESTS)

		x->mac_gmii_tx_proto_engine++;

	if (value & GMAC_DEBUG_RXFSTS_MASK) {

		u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)

			     >> GMAC_DEBUG_RRCSTS_SHIFT;

		u32 rxfsts = FIELD_GET(GMAC_DEBUG_RXFSTS_MASK, value);



		if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)

			x->mtl_rx_fifo_fill_level_full++;
@@ -420,8 +418,7 @@ static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr, 
			x->mtl_rx_fifo_fill_level_empty++;

	}

	if (value & GMAC_DEBUG_RRCSTS_MASK) {

		u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>

			     GMAC_DEBUG_RRCSTS_SHIFT;

		u32 rrcsts = FIELD_GET(GMAC_DEBUG_RRCSTS_MASK, value);



		if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)

			x->mtl_rx_fifo_read_ctrl_flush++;
@@ -435,8 +432,8 @@ static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr, 
	if (value & GMAC_DEBUG_RWCSTS)

		x->mtl_rx_fifo_ctrl_active++;

	if (value & GMAC_DEBUG_RFCFCSTS_MASK)

		x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)

					    >> GMAC_DEBUG_RFCFCSTS_SHIFT;

		x->mac_rx_frame_ctrl_fifo = FIELD_GET(GMAC_DEBUG_RFCFCSTS_MASK,

						      value);

	if (value & GMAC_DEBUG_RPESTS)

		x->mac_gmii_rx_proto_engine++;

}
@@ -534,7 +531,7 @@ void dwmac1000_timestamp_interrupt(struct stmmac_priv *priv) 
	if (!(priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN))

		return;



	num_snapshot = (ts_status & GMAC3_X_ATSNS) >> GMAC3_X_ATSNS_SHIFT;

	num_snapshot = FIELD_GET(GMAC3_X_ATSNS, ts_status);



	for (i = 0; i < num_snapshot; i++) {

		read_lock_irqsave(&priv->ptp_lock, flags);