Commit 842c3755 authored by Jiasheng Jiang's avatar Jiasheng Jiang Committed by William Breathitt Gray
Browse files

counter: stm32-timer-cnt: Add check for clk_enable() 



Add check for the return value of clk_enable() in order to catch the
potential exception.

Fixes: c5b84255 ("counter: stm32-timer-cnt: add power management support")
Fixes: ad29937e ("counter: Add STM32 Timer quadrature encoder")
Signed-off-by: default avatarJiasheng Jiang <jiashengjiangcool@gmail.com>
Link: https://lore.kernel.org/r/20241104191825.40155-1-jiashengjiangcool@gmail.com


Signed-off-by: default avatarWilliam Breathitt Gray <wbg@kernel.org>
parent 147359e2

drivers/counter/stm32-timer-cnt.c

+13 −3
Original line number Diff line number Diff line
@@ -214,11 +214,17 @@ static int stm32_count_enable_write(struct counter_device *counter, 
{

	struct stm32_timer_cnt *const priv = counter_priv(counter);

	u32 cr1;

	int ret;



	if (enable) {

		regmap_read(priv->regmap, TIM_CR1, &cr1);

		if (!(cr1 & TIM_CR1_CEN))

			clk_enable(priv->clk);

		if (!(cr1 & TIM_CR1_CEN)) {

			ret = clk_enable(priv->clk);

			if (ret) {

				dev_err(counter->parent, "Cannot enable clock %d\n", ret);

				return ret;

			}

		}



		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,

				   TIM_CR1_CEN);
@@ -817,7 +823,11 @@ static int __maybe_unused stm32_timer_cnt_resume(struct device *dev) 
		return ret;



	if (priv->enabled) {

		clk_enable(priv->clk);

		ret = clk_enable(priv->clk);

		if (ret) {

			dev_err(dev, "Cannot enable clock %d\n", ret);

			return ret;

		}



		/* Restore registers that may have been lost */

		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);